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公开(公告)号：US07577779B2
公开(公告)日：2009-08-18
申请号：US11353904
申请日：2006-02-14
CPC分类号： G06F13/4221
摘要： Methods and systems for a RFIC master are disclosed. Aspects of one method may include configuring an on-chip programmable device that may function as a master on a bus that has at least one device interface, for example, RFIC interface, coupled to the bus. The on-chip programmable device may generate at least one signal to control at least one device coupled to at least one device interface. The on-chip programmable device may communicate the generated signal via the bus upon receiving an input timer signal and may be configured by writing at least one event data and an index-sample data to the on-chip programmable device. The index-sample data may comprise at least a count value and an event data index. When the count value equals a value of the timer signal, event data may be fetched and executed starting with the one specified by the event data index.
摘要翻译： 公开了RFIC主机的方法和系统。 一种方法的方面可以包括配置片上可编程设备，该片上可编程设备可以在总线上起主机的作用，该总线具有耦合到总线的至少一个设备接口，例如RFIC接口。 片上可编程器件可以产生至少一个信号以控制耦合到至少一个器件接口的至少一个器件。 片上可编程设备可以在接收到输入定时器信号时经由总线通信所生成的信号，并且可以通过将至少一个事件数据和索引样本数据写入到片上可编程设备来配置。 索引样本数据可以包括至少计数值和事件数据索引。 当计数值等于定时器信号的值时，可以从事件数据索引指定的事件数据开始获取并执行事件数据。
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2.发明授权Method and system for dynamically programmable serial/parallel bus interface 有权动态可编程串行/并行总线接口的方法和系统公开(公告)号：US08429320B2
公开(公告)日：2013-04-23
申请号：US12755755
申请日：2010-04-07
申请人： Andrew du Preez , Yi Zhou
发明人： Andrew du Preez , Yi Zhou
IPC分类号： G06F13/00
CPC分类号： G06F13/4286 , G06F13/42 , Y02D10/14 , Y02D10/151
摘要： Aspects of a method and system for dynamically programmable serial/parallel bus interface may include performing in a first communication device coupled to a communication bus, attaching communication protocol information to a data signal for each data transaction with one or more other communication devices communicatively coupled to the communication bus. The one or more other communication devices may be controlled utilizing the attached communication protocol information. The communication protocol information may be dynamically adjusted and/or adaptively adjusted. The communication bus may be a serial or parallel communication bus. The serial communication bus may be a two-wire, three-wire, or four-wire bus. The attached communication protocol information comprises a multi-wire protocol, a 3-wire protocol, a Serial Peripheral Interface (SPI) protocol, a System Power Management Interface (SPMI), or an RF Bus protocol.
摘要翻译： 用于动态可编程串行/并行总线接口的方法和系统的方面可以包括在耦合到通信总线的第一通信设备中执行，将通信协议信息附加到用于每个数据事务的数据信号，其中一个或多个其他通信设备通信地耦合到 通讯总线。 可以利用附加的通信协议信息来控制一个或多个其他通信设备。 可以动态地调整和/或自适应地调整通信协议信息。 通信总线可以是串行或并行通信总线。 串行通信总线可以是双线，三线或四线总线。 附加的通信协议信息包括多线协议，3线协议，串行外设接口（SPI）协议，系统电源管理接口（SPMI）或RF总线协议。
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公开(公告)号：US20120263030A1
公开(公告)日：2012-10-18
申请号：US13532410
申请日：2012-06-25
申请人： Mark Hahm , Wei Luo , Thirunathan Sutharsan , Andrew du Preez , Bin Liu , Jun Wu , Severine Catreux-Erceg , Shuangquan Wang
发明人： Mark Hahm , Wei Luo , Thirunathan Sutharsan , Andrew du Preez , Bin Liu , Jun Wu , Severine Catreux-Erceg , Shuangquan Wang
IPC分类号： H04W88/00
CPC分类号： H04B1/71075 , H04B1/7115 , H04B1/712 , H04B2201/70702
摘要： Aspects of a method and system for a programmable interference suppression module may include receiving a communication signal comprising one or more desired signal, and one or more undesired signals. The communication signal may be utilized to generate estimated channel state information. The estimated channel state information may be formatted for use in interference suppression. A reduced interference signal may be generated from a delayed version of said communications signal and the estimated channel state information, wherein the one or more undesired signals may be attenuated. The reduced interference signal may be formatted for post-processing. The desired signals may comprise WCDMA and/or HSDPA signals, and the undesired signals may be inter-cell and/or intra-cell interference. Further processing may comprise HSDPA processing and/or RAKE finger processing. The communication signal may be a Universal Mobile Telecommunication System (UMTS) compliant signal.
摘要翻译： 用于可编程干扰抑制模块的方法和系统的方面可以包括接收包括一个或多个期望信号的通信信号以及一个或多个不需要的信号。 通信信号可用于产生估计的信道状态信息。 估计的信道状态信息可以被格式化以用于干扰抑制。 可以从所述通信信号的延迟版本和所估计的信道状态信息产生减小的干扰信号，其中所述一个或多个不需要的信号可以被衰减。 减小的干扰信号可以被格式化用于后处理。 期望的信号可以包括WCDMA和/或HSDPA信号，并且不期望的信号可以是小区间和/或小区内干扰。 进一步的处理可以包括HSDPA处理和/或RAKE手指处理。 通信信号可以是符合通用移动通信系统（UMTS）的信号。
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公开(公告)号：US08161217B2
公开(公告)日：2012-04-17
申请号：US13186311
申请日：2011-07-19
CPC分类号： G06F13/4221
摘要： Methods and systems for a RFIC master are disclosed. Aspects of one method may include configuring an on-chip programmable device that may function as a master on a bus that has at least one device interface, for example, RFIC interface, coupled to the bus. The on-chip programmable device may generate at least one signal to control at least one device coupled to at least one device interface. The on-chip programmable device may communicate the generated signal via the bus upon receiving an input timer signal and may be configured by writing at least one event data and an index-sample data to the on-chip programmable device. The index-sample data may comprise at least a count value and an event data index. When the count value equals a value of the timer signal, event data may be fetched and executed starting with the one specified by the event data index.
摘要翻译： 公开了RFIC主机的方法和系统。 一种方法的方面可以包括配置片上可编程设备，该片上可编程设备可以在总线上起主机的作用，该总线具有耦合到总线的至少一个设备接口，例如RFIC接口。 片上可编程器件可以产生至少一个信号以控制耦合到至少一个器件接口的至少一个器件。 片上可编程设备可以在接收到输入定时器信号时经由总线通信所生成的信号，并且可以通过将至少一个事件数据和索引样本数据写入到片上可编程设备来配置。 索引样本数据可以包括至少计数值和事件数据索引。 当计数值等于定时器信号的值时，可以从事件数据索引指定的事件数据开始获取并执行事件数据。
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公开(公告)号：US07949012B2
公开(公告)日：2011-05-24
申请号：US11861700
申请日：2007-09-26
申请人： Li Fung Chang , Andrew Du Preez
发明人： Li Fung Chang , Andrew Du Preez
IPC分类号： H04J3/24
CPC分类号： H04L12/66 , H04L1/1607 , H04L1/1874 , H04L63/0428 , H04W12/02 , H04W84/042
摘要： A combined data packing, cipher and multiplexing engine operable to support high speed uplink packet access (HS-UPA) within user equipment (UE) is provided. This combined cipher multiplexing engine includes a master port, a radio link control (RLC) data packer, and a cipher multiplexing processing module. The master port couples to an advanced microprocessor bus architecture (AMBA) high speed buss (AHB) on which control information for the combined cipher and multiplexing engine is provided. The RLC couples to the master port and receives RLC service data units (SDUs) from the AHB. Then the RLC data packer may concatenate or segment RLC SDUs into RLC packet data units (PDUs) which are stored for use by a cipher multiplexing processing module. The cipher multiplexing processing module retrieves the RLC PDU from the RLC PDU buffer and ciphers to produce ciphered data, if cipher is enabled and multiplexes the ciphered/non-ciphered data together with the RLC header, MAC-es header, MAC-e header and enters the multiplexed results to a hybrid automatic repeat request (HARQ) buffer. A protocol stack executed within the UE activates and provides an array on the formation of the RLC PDU, RLC header information to the combined cipher and multiplexing engine for RLC PDU ciphering and medium access control (MAC) multiplexing of the enhanced data transport channel (E-DCH).
摘要翻译： 提供可操作以支持用户设备（UE）内的高速上行链路分组接入（HS-UPA）的组合数据打包，加密和复用引擎。 该组合密码复用引擎包括主端口，无线链路控制（RLC）数据封包器和密码复用处理模块。 主端口耦合到提供组合密码和复用引擎的控制信息的高级微处理器总线架构（AMBA）高速总线（AHB）。 RLC耦合到主端口并从AHB接收RLC服务数据单元（SDU）。 然后，RLC数据打包器可以将RLC SDU连接或分段成存储供密码复用处理模块使用的RLC分组数据单元（PDU）。 密码复用处理模块从RLC PDU缓冲器中检索RLC PDU并加密以产生加密数据，如果密码被使能，并将加密/非加密数据与RLC报头，MAC-es报头，MAC-e报头和 将复用结果输入到混合自动重传请求（HARQ）缓冲器。 在UE内执行的协议栈激活并提供RLC PDU的形成的阵列，RLC头信息到组合密码和复用引擎，用于RLC PDU加密和增强型数据传输信道（E）的介质访问控制（MAC）复用 -DCH）。
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公开(公告)号：US08208856B2
公开(公告)日：2012-06-26
申请号：US12686623
申请日：2010-01-13
申请人： Mark Hahm , Wei Luo , Thirunathan Sutharsan , Andrew du Preez , Bin Liu , Jun Wu , Severine Catreux-Erceg , Shuangquan Wang
发明人： Mark Hahm , Wei Luo , Thirunathan Sutharsan , Andrew du Preez , Bin Liu , Jun Wu , Severine Catreux-Erceg , Shuangquan Wang
IPC分类号： H04B1/00
CPC分类号： H04B1/71075 , H04B1/7115 , H04B1/712 , H04B2201/70702
摘要： Aspects of a method and system for a programmable interference suppression module may include receiving a communication signal comprising one or more desired signal, and one or more undesired signals. The communication signal may be utilized to generate estimated channel state information. The estimated channel state information may be formatted for use in interference suppression. A reduced interference signal may be generated from a delayed version of said communications signal and the estimated channel state information, wherein the one or more undesired signals may be attenuated. The reduced interference signal may be formatted for post-processing. The desired signals may comprise WCDMA and/or HSDPA signals, and the undesired signals may be inter-cell and/or intra-cell interference. Further processing may comprise HSDPA processing and/or RAKE finger processing. The communication signal may be a Universal Mobile Telecommunication System (UMTS) compliant signal.
摘要翻译： 用于可编程干扰抑制模块的方法和系统的方面可以包括接收包括一个或多个期望信号的通信信号以及一个或多个不需要的信号。 通信信号可用于产生估计的信道状态信息。 估计的信道状态信息可以被格式化以用于干扰抑制。 可以从所述通信信号的延迟版本和所估计的信道状态信息产生减小的干扰信号，其中所述一个或多个不需要的信号可以被衰减。 减小的干扰信号可以被格式化用于后处理。 期望的信号可以包括WCDMA和/或HSDPA信号，并且不期望的信号可以是小区间和/或小区内干扰。 进一步的处理可以包括HSDPA处理和/或RAKE手指处理。 通信信号可以是符合通用移动通信系统（UMTS）的信号。
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公开(公告)号：US07984216B2
公开(公告)日：2011-07-19
申请号：US12543008
申请日：2009-08-18
CPC分类号： G06F13/4221
摘要： Methods and systems for a RFIC master are disclosed. Aspects of one method may include configuring an on-chip programmable device that may function as a master on a bus that has at least one device interface, for example, RFIC interface, coupled to the bus. The on-chip programmable device may generate at least one signal to control at least one device coupled to at least one device interface. The on-chip programmable device may communicate the generated signal via the bus upon receiving an input timer signal and may be configured by writing at least one event data and an index-sample data to the on-chip programmable device. The index-sample data may comprise at least a count value and an event data index. When the count value equals a value of the timer signal, event data may be fetched and executed starting with the one specified by the event data index.
摘要翻译： 公开了RFIC主机的方法和系统。 一种方法的方面可以包括配置片上可编程设备，该片上可编程设备可以在总线上起主机的作用，该总线具有耦合到总线的至少一个设备接口，例如RFIC接口。 片上可编程器件可以产生至少一个信号以控制耦合到至少一个器件接口的至少一个器件。 片上可编程设备可以在接收到输入定时器信号时经由总线通信所生成的信号，并且可以通过将至少一个事件数据和索引样本数据写入到片上可编程设备来配置。 索引样本数据可以包括至少计数值和事件数据索引。 当计数值等于定时器信号的值时，可以从事件数据索引指定的事件数据开始获取并执行事件数据。
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8.发明申请METHOD AND SYSTEM FOR DYNAMICALLY PROGRAMMABLE SERIAL/PARALLEL BUS INTERFACE 有权用于动态可编程序列/并行总线接口的方法和系统公开(公告)号：US20110153887A1
公开(公告)日：2011-06-23
申请号：US12755755
申请日：2010-04-07
申请人： Andrew du Preez , Yi Zhou
发明人： Andrew du Preez , Yi Zhou
IPC分类号： G06F13/42
CPC分类号： G06F13/4286 , G06F13/42 , Y02D10/14 , Y02D10/151
摘要： Aspects of a method and system for dynamically programmable serial/parallel bus interface may include performing in a first communication device coupled to a communication bus, attaching communication protocol information to a data signal for each data transaction with one or more other communication devices communicatively coupled to the communication bus. The one or more other communication devices may be controlled utilizing the attached communication protocol information. The communication protocol information may be dynamically adjusted and/or adaptively adjusted. The communication bus may be a serial or parallel communication bus. The serial communication bus may be a two-wire, three-wire, or four-wire bus. The attached communication protocol information comprises a multi-wire protocol, a 3-wire protocol, a Serial Peripheral Interface (SPI) protocol, a System Power Management Interface (SPMI), or an RF Bus protocol.
摘要翻译： 用于动态可编程串行/并行总线接口的方法和系统的方面可以包括在耦合到通信总线的第一通信设备中执行，将通信协议信息附加到用于每个数据事务的数据信号，其中一个或多个其他通信设备通信地耦合到 通讯总线。 可以利用附加的通信协议信息来控制一个或多个其他通信设备。 可以动态地调整和/或自适应地调整通信协议信息。 通信总线可以是串行或并行通信总线。 串行通信总线可以是双线，三线或四线总线。 附加的通信协议信息包括多线协议，3线协议，串行外设接口（SPI）协议，系统电源管理接口（SPMI）或RF总线协议。
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公开(公告)号：US20110103530A1
公开(公告)日：2011-05-05
申请号：US12611810
申请日：2009-11-03
申请人： Wei Luo , Karthik Rajagopalan , Andrew du Preez , Bin Liu , Shuangquan Wang
发明人： Wei Luo , Karthik Rajagopalan , Andrew du Preez , Bin Liu , Shuangquan Wang
IPC分类号： H04B1/10
CPC分类号： H04B1/7107
摘要： Aspects of a method and system for compensation of interference cancellation delay are provided. In this regard, a wireless communication device may receive one or more signals and may be operable to select, whether dynamically or statically, a processing path for processing the one or more received signals. The selected processing path may comprise one of an interference cancellation processing path and a pass-through processing path. A delay introduced by the pass-through processing path may be approximately equal to a processing delay introduced by the interference cancellation processing path. The one or more received signals may comprise HSDPA signals. The selection of processing path may be based on a measure of interference present in the one or more received signals.
摘要翻译： 提供了一种用于补偿干扰消除延迟的方法和系统。 在这方面，无线通信设备可以接收一个或多个信号，并且可以可操作地动态地或静态地选择用于处理一个或多个接收信号的处理路径。 所选择的处理路径可以包括干扰消除处理路径和直通处理路径之一。 由直通处理路径引入的延迟可以近似等于由干扰消除处理路径引入的处理延迟。 一个或多个接收信号可以包括HSDPA信号。 处理路径的选择可以基于存在于一个或多个接收信号中的干扰的度量。
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10.发明申请HIGH-SPEED UPLINK PACKET ACCESS (HSUPA) CIPHER MULTIPLEXING ENGINE 有权高速上链包接入（HSUPA）CIPHER MULTIPLEXING发动机公开(公告)号：US20090034507A1
公开(公告)日：2009-02-05
申请号：US11861700
申请日：2007-09-26
申请人： Li Fung Chang , Andrew Du Preez
发明人： Li Fung Chang , Andrew Du Preez
CPC分类号： H04L12/66 , H04L1/1607 , H04L1/1874 , H04L63/0428 , H04W12/02 , H04W84/042
摘要： A combined data packing, cipher and multiplexing engine operable to support high speed uplink packet access (HS-UPA) within user equipment (UE) is provided. This combined cipher multiplexing engine includes a master port, a radio link control (RLC) data packer, and a cipher multiplexing processing module. The master port couples to an advanced microprocessor bus architecture (AMBA) high speed buss (AHB) on which control information for the combined cipher and multiplexing engine is provided. The RLC couples to the master port and receives RLC service data units (SDUs) from the AHB. Then the RLC data packer may concatenate or segment RLC SDUs into RLC packet data units (PDUs) which are stored for use by a cipher multiplexing processing module. The cipher multiplexing processing module retrieves the RLC PDU from the RLC PDU buffer and ciphers to produce ciphered data, if cipher is enabled and multiplexes the ciphered/non-ciphered data together with the RLC header, MAC-es header, MAC-e header and enters the multiplexed results to a hybrid automatic repeat request (HARQ) buffer. A protocol stack executed within the UE activates and provides an array on the formation of the RLC PDU, RLC header information to the combined cipher and multiplexing engine for RLC PDU ciphering and medium access control (MAC) multiplexing of the enhanced data transport channel (E-DCH).
摘要翻译： 提供可操作以支持用户设备（UE）内的高速上行链路分组接入（HS-UPA）的组合数据打包，加密和复用引擎。 该组合密码复用引擎包括主端口，无线链路控制（RLC）数据封包器和密码复用处理模块。 主端口耦合到提供组合密码和复用引擎的控制信息的高级微处理器总线架构（AMBA）高速总线（AHB）。 RLC耦合到主端口并从AHB接收RLC服务数据单元（SDU）。 然后，RLC数据打包器可以将RLC SDU连接或分段成存储供密码复用处理模块使用的RLC分组数据单元（PDU）。 密码复用处理模块从RLC PDU缓冲器中检索RLC PDU并加密以产生加密数据，如果密码被使能，并将加密/非加密数据与RLC报头，MAC-es报头，MAC-e报头和 将复用结果输入到混合自动重传请求（HARQ）缓冲器。 在UE内执行的协议栈激活并提供RLC PDU的形成的阵列，RLC头信息到组合密码和复用引擎，用于RLC PDU加密和增强型数据传输信道（E）的介质访问控制（MAC）复用 -DCH）。
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