公开(公告)号：US08503588B2

公开(公告)日：2013-08-06

申请号：US12611810

申请日：2009-11-03

Applicant: Wei Luo ,  Karthik Rajagopalan ,  Andrew du Preez ,  Bin Liu ,  Shuangquan Wang

Inventor： Wei Luo ,  Karthik Rajagopalan ,  Andrew du Preez ,  Bin Liu ,  Shuangquan Wang

IPC: H04B1/10 ,  H04L25/08

CPC classification number: H04B1/7107

Abstract: Aspects of a method and system for compensation of interference cancellation delay are provided. In this regard, a wireless communication device may receive one or more signals and may be operable to select, whether dynamically or statically, a processing path for processing the one or more received signals. The selected processing path may comprise one of an interference cancellation processing path and a pass-through processing path. A delay introduced by the pass-through processing path may be approximately equal to a processing delay introduced by the interference cancellation processing path. The one or more received signals may comprise HSDPA signals. The selection of processing path may be based on a measure of interference present in the one or more received signals.

Abstract translation: 提供了一种用于补偿干扰消除延迟的方法和系统。 在这方面，无线通信设备可以接收一个或多个信号，并且可以可操作地动态地或静态地选择用于处理一个或多个接收信号的处理路径。 所选择的处理路径可以包括干扰消除处理路径和直通处理路径之一。 由直通处理路径引入的延迟可以近似等于由干扰消除处理路径引入的处理延迟。 一个或多个接收信号可以包括HSDPA信号。 处理路径的选择可以基于存在于一个或多个接收信号中的干扰的度量。

公开(公告)号：US07799647B2

公开(公告)日：2010-09-21

申请号：US11831394

申请日：2007-07-31

Applicant: Ravindranath Droopad ,  Matthias Passlack ,  Karthik Rajagopalan

Inventor： Ravindranath Droopad ,  Matthias Passlack ,  Karthik Rajagopalan

IPC: H01L21/336 ,  H01L31/00

CPC classification number: H01L29/155 ,  H01L29/66462

Abstract: A method of forming a semiconductor structure includes forming a channel layer; forming a superlattice barrier layer overlying the channel layer, and forming a gate dielectric overlying the superlattice barrier layer. The superlattice barrier layer includes alternating first and second layers of barrier material. In addition, the superlattice barrier layer is configured for increasing a transconductance of the semiconductor device by at least a factor of three over a semiconductor device absent such superlattice barrier layer.

Abstract translation: 形成半导体结构的方法包括形成沟道层; 形成覆盖所述沟道层的超晶格势垒层，以及形成覆盖所述超晶格势垒层的栅极电介质。 超晶格势垒层包括交替的第一和第二层屏障材料。 此外，超晶格势垒层被配置为在没有这种超晶格势垒层的半导体器件上将半导体器件的跨导增加至少三分之一。

公开(公告)号：US20090032802A1

公开(公告)日：2009-02-05

申请号：US11831394

申请日：2007-07-31

Applicant: Ravindranath Droopad ,  Matthias Passlack ,  Karthik Rajagopalan

Inventor： Ravindranath Droopad ,  Matthias Passlack ,  Karthik Rajagopalan

IPC: H01L29/15 ,  H01L21/336

CPC classification number: H01L29/155 ,  H01L29/66462

Abstract: A method of forming a semiconductor structure comprises forming a channel layer; forming a superlattice barrier layer overlying the channel layer, and forming a gate dielectric overlying the superlattice barrier layer. The superlattice barrier layer includes a plurality of alternating first and second layers of barrier material. In addition, the superlattice barrier layer is configured for increasing a transconductance of the semiconductor device by at least a factor of three over a semiconductor device absent such superlattice barrier layer.

Abstract translation: 形成半导体结构的方法包括形成沟道层; 形成覆盖所述沟道层的超晶格势垒层，以及形成覆盖所述超晶格势垒层的栅极电介质。 超晶格阻挡层包括多个交替的第一和第二层屏障材料。 此外，超晶格势垒层被配置为在没有这种超晶格势垒层的半导体器件上将半导体器件的跨导增加至少三分之一。

公开(公告)号：US20070090405A1

公开(公告)日：2007-04-26

申请号：US11236187

申请日：2005-09-27

Applicant: Matthias Passlack ,  Ravindranath Droopad ,  Karthik Rajagopalan

Inventor： Matthias Passlack ,  Ravindranath Droopad ,  Karthik Rajagopalan

IPC: H01L23/58

CPC classification number: H01L29/66462 ,  H01L21/02178 ,  H01L21/02222 ,  H01L21/02362 ,  H01L21/28264 ,  H01L21/318 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor structure comprises providing an insulator layer overlying a III-V compound substrate, the insulator layer having a surface charge layer, the surface charge layer having a deleterious performance effect on the underlying layer or layers of the III-V compound substrate. The method further comprises transforming the surface charge layer into a passivated surface layer, wherein the passivated surface layer reduces the deleterious performance effect on the underlying layer or layers.

Abstract translation: 形成半导体结构的方法包括提供覆盖III-V复合衬底的绝缘体层，所述绝缘体层具有表面电荷层，所述表面电荷层对III-V族化合物的下层或多层具有有害的性能作用 基质。 该方法还包括将表面电荷层转化为钝化表面层，其中钝化表面层减少对下层或下层的有害性能影响。

公开(公告)号：US07642182B2

公开(公告)日：2010-01-05

申请号：US11972475

申请日：2008-01-10

Applicant: Agni Mitra ,  Darrell G. Hill ,  Karthik Rajagopalan ,  Adolfo C. Reyes

Inventor： Agni Mitra ,  Darrell G. Hill ,  Karthik Rajagopalan ,  Adolfo C. Reyes

IPC: H01L21/44

CPC classification number: H01L23/62 ,  H01L27/0248 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  Y10T29/413 ,  Y10T29/49204 ,  H01L2924/00

Abstract: Methods and apparatus are provided for ESD protection of integrated passive devices (IPDs). The apparatus comprises one or more IPDs having terminals or other elements potentially exposed to ESD transients coupled by charge leakage resistances having resistance values much larger than the ordinary impedance of the IPDs at the operating frequency of interest. When the IPD is built on a semi-insulating substrate, various elements of the IPD are coupled to the substrate by spaced-apart connections so that the substrate itself provides the high value resistances coupling the elements, but this is not essential. When applied to an IPD RF coupler, the ESD tolerance increased by over 70%. The invented arrangement can also be applied to active devices and integrated circuits and to IPDs with conductive or insulating substrates.

Abstract translation: 为集成无源器件（IPD）的ESD保护提供了方法和设备。 该装置包括一个或多个IPD，其具有潜在地暴露于ESD瞬变的端子或其他元件，其通过电荷泄漏电阻耦合，其电阻值比在感兴趣的工作频率下的IPD的普通阻抗大得多。 当IPD构建在半绝缘基板上时，IPD的各种元件通过间隔开的连接件耦合到基板，使得基板本身提供耦合元件的高价值电阻，但这不是必须的。 当应用于IPD RF耦合器时，ESD耐受性提高了70％以上。 本发明的布置还可以应用于有源器件和集成电路以及具有导电或绝缘衬底的IPD。

公开(公告)号：US07335955B2

公开(公告)日：2008-02-26

申请号：US11300710

申请日：2005-12-14

Applicant: Agni Mitra ,  Darrell G. Hill ,  Karthik Rajagopalan ,  Adolfo C. Reyes

Inventor： Agni Mitra ,  Darrell G. Hill ,  Karthik Rajagopalan ,  Adolfo C. Reyes

IPC: H01L23/62

CPC classification number: H01L23/62 ,  H01L27/0248 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  Y10T29/413 ,  Y10T29/49204 ,  H01L2924/00

Abstract: Methods and apparatus are provided for ESD protection of integrated passive devices (IPDs). The apparatus comprises one or more IPDs having terminals or other elements potentially exposed to ESD transients coupled by charge leakage resistances having resistance values much larger than the ordinary impedance of the IPDs at the operating frequency of interest. When the IPD is built on a semi-insulating substrate, various elements of the IPD are coupled to the substrate by spaced-apart connections so that the substrate itself provides the high value resistances coupling the elements, but this is not essential. When applied to an IPD RF coupler, the ESD tolerance increased by over 70%. The invented arrangement can also be applied to active devices and integrated circuits and to IPDs with conductive or insulating substrates.

Abstract translation: 为集成无源器件（IPD）的ESD保护提供了方法和设备。 该装置包括一个或多个IPD，其具有潜在地暴露于ESD瞬变的端子或其他元件，其通过电荷泄漏电阻耦合，其电阻值比在感兴趣的工作频率下的IPD的普通阻抗大得多。 当IPD构建在半绝缘基板上时，IPD的各种元件通过间隔开的连接件耦合到基板，使得基板本身提供耦合元件的高价值电阻，但这不是必须的。 当应用于IPD RF耦合器时，ESD耐受性提高了70％以上。 本发明的布置还可以应用于有源器件和集成电路以及具有导电或绝缘衬底的IPD。

公开(公告)号：US08331421B2

公开(公告)日：2012-12-11

申请号：US12543283

申请日：2009-08-18

Applicant: Hongwei Kong ,  Karthik Rajagopalan

Inventor： Hongwei Kong ,  Karthik Rajagopalan

IPC: H04B1/00

CPC classification number: H04B1/7117 ,  H04B1/70757

Abstract: Aspects of a method and system for a delay-locked loop for closely spaced multipath may include determining a difference signal computed from one or more early energies and one or more late energies associated with one or more channel taps selected from a plurality of channel taps. A fat finger timing may be adjusted based on the difference signal, the fat finger comprising the plurality of channel taps that are spaced contiguously at chip period intervals. The one or more early energies and the one or more late energies may be determined based on an offset of Tc/2 or 3Tc/8, where Tc denotes the chip period interval. The offset may be measured from an energy peak associated with a multipath component that may be associated with the fat finger.

Abstract translation: 用于紧密间隔多路径的延迟锁定环路的方法和系统的方面可以包括确定从一个或多个早期能量计算的差分信号和与从多个信道抽头中选择的一个或多个信道抽头相关联的一个或多个后期能量。 可以基于差分信号来调整胖手指定时，该胖指包括以码片周期间隔连续间隔的多个信道抽头。 可以基于Tc / 2或3Tc / 8的偏移来确定一个或多个早期能量和一个或多个后期能量，其中Tc表示芯片周期间隔。 可以从与可能与脂肪手指相关联的多径分量相关联的能量峰值来测量偏移。

公开(公告)号：US20110103530A1

公开(公告)日：2011-05-05

申请号：US12611810

申请日：2009-11-03

Applicant: Wei Luo ,  Karthik Rajagopalan ,  Andrew du Preez ,  Bin Liu ,  Shuangquan Wang

Inventor： Wei Luo ,  Karthik Rajagopalan ,  Andrew du Preez ,  Bin Liu ,  Shuangquan Wang

IPC: H04B1/10

CPC classification number: H04B1/7107

Abstract: Aspects of a method and system for compensation of interference cancellation delay are provided. In this regard, a wireless communication device may receive one or more signals and may be operable to select, whether dynamically or statically, a processing path for processing the one or more received signals. The selected processing path may comprise one of an interference cancellation processing path and a pass-through processing path. A delay introduced by the pass-through processing path may be approximately equal to a processing delay introduced by the interference cancellation processing path. The one or more received signals may comprise HSDPA signals. The selection of processing path may be based on a measure of interference present in the one or more received signals.

Abstract translation: 提供了一种用于补偿干扰消除延迟的方法和系统。 在这方面，无线通信设备可以接收一个或多个信号，并且可以可操作地动态地或静态地选择用于处理一个或多个接收信号的处理路径。 所选择的处理路径可以包括干扰消除处理路径和直通处理路径之一。 由直通处理路径引入的延迟可以近似等于由干扰消除处理路径引入的处理延迟。 一个或多个接收信号可以包括HSDPA信号。 处理路径的选择可以基于存在于一个或多个接收信号中的干扰的度量。

公开(公告)号：US20110043386A1

公开(公告)日：2011-02-24

申请号：US12543283

申请日：2009-08-18

Applicant: Hongwei Kong ,  Karthik Rajagopalan

Inventor： Hongwei Kong ,  Karthik Rajagopalan

IPC: H03K17/94

CPC classification number: H04B1/7117 ,  H04B1/70757

Abstract: Aspects of a method and system for a delay-locked loop for closely spaced multipath may include determining a difference signal computed from one or more early energies and one or more late energies associated with one or more channel taps selected from a plurality of channel taps. A fat finger timing may be adjusted based on the difference signal, the fat finger comprising the plurality of channel taps that are spaced contiguously at chip period intervals. The one or more early energies and the one or more late energies may be determined based on an offset of Tc/2 or 3Tc/8, where Tc denotes the chip period interval. The offset may be measured from an energy peak associated with a multipath component that may be associated with the fat finger.

Abstract translation: 用于紧密间隔多路径的延迟锁定环路的方法和系统的方面可以包括确定从一个或多个早期能量计算的差分信号和与从多个信道抽头中选择的一个或多个信道抽头相关联的一个或多个后期能量。 可以基于差分信号来调整胖手指定时，该胖指包括以码片周期间隔连续间隔的多个信道抽头。 可以基于Tc / 2或3Tc / 8的偏移来确定一个或多个早期能量和一个或多个后期能量，其中Tc表示芯片周期间隔。 可以从与可能与脂肪手指相关联的多径分量相关联的能量峰值来测量偏移。

公开(公告)号：US20080102607A1

公开(公告)日：2008-05-01

申请号：US11554859

申请日：2006-10-31

Applicant: Matthias Passlack ,  Ravindranath Droopad ,  Karthik Rajagopalan

Inventor： Matthias Passlack ,  Ravindranath Droopad ,  Karthik Rajagopalan

IPC: H01L21/20

CPC classification number: H01L29/66924 ,  H01L29/2003

Abstract: A method of forming a III-V compound semiconductor structure (10) comprises providing a III-V compound semiconductor substrate including a semi-insulating substrate (12) having at least one epitaxial layer formed thereon and further having a gate insulator (14) overlying the at least one epitaxial layer. The at least one epitaxial layer formed on the semi-insulating substrate comprises an epi-structure suitable for use in the formation of a channel of a III-V compound semiconductor MOSFET device, wherein the channel (30) having a first polarity. The method further comprises forming a charge layer (22) at a surface of the gate insulator, the charge layer having a second polarity, wherein the second polarity is opposite to the first polarity.

Abstract translation: 一种形成III-V族化合物半导体结构（10）的方法包括：提供一种III-V族化合物半导体衬底，该III-V族化合物半导体衬底包括半导体衬底（12），该半绝缘衬底具有形成在其上的至少一个外延层，并且还具有覆盖 所述至少一个外延层。 形成在半绝缘衬底上的至少一个外延层包括适于用于形成III-V族化合物半导体MOSFET器件的沟道的外延结构，其中，具有第一极性的沟道（30）。 该方法还包括在栅极绝缘体的表面形成电荷层（22），电荷层具有第二极性，其中第二极性与第一极性相反。