公开(公告)号：US20250131523A1

公开(公告)日：2025-04-24

申请号：US18918880

申请日：2024-10-17

Applicant: Arm Limited

Inventor： Frank Klaeboe Langtind ,  Olof Henrik Uhrenholt

IPC: G06T1/20

Abstract: A tile-based graphics processor performs first and second processing passes to generate a render output. The first processing pass generates data that is used in the second processing pass to determine which primitives to process for which rendering tiles. The first processing pass is performed by a geometry processing control unit assembling primitives, and one or more programmable processing units transforming geometry data defining the primitives, and processing the transformed geometry data to generate the data.

公开(公告)号：US12272105B2

公开(公告)日：2025-04-08

申请号：US18067271

申请日：2022-12-16

Applicant: Arm Limited

Inventor： Olof Henrik Uhrenholt

IPC: G06T1/60 ,  G06T1/20 ,  G06T9/00

Abstract: A data processing system comprises a processor that generates data elements of an array of data and stores the data elements in the one or more local buffers. When a set of data elements that corresponds to less than an entire region of plural separate regions that the array of data is divided into is to be written from the one or more local buffers to memory, the processor may encode the set of data elements so as to produce an encoded block of data and store the encoded block of data in memory by: writing body data to one of a first body buffer and a second body buffer, wherein the set of data elements is encoded using a first encoding for which header information descriptive of the body data will be independent of the values of the data elements being encoded.

公开(公告)号：US12271320B2

公开(公告)日：2025-04-08

申请号：US17906625

申请日：2021-01-26

Applicant: ARM LIMITED

Inventor： Jason Parker ,  Andrew Brookfield Swaine ,  Yuval Elad ,  Martin Weidmann

IPC: G06F12/14 ,  G06F12/0808 ,  G06F12/1045

Abstract: Address translation circuitry (16) translates a virtual address specified by a memory access request issued by requester circuitry into a target physical address (PA). Requester-side filtering circuitry (20) performs a granule protection lookup based on the target PA and a selected physical address space (PAS) associated with the memory access request, to determine whether to allow the memory access request to be passed to a cache or interconnect. In the granule protection lookup, the requester-side filtering circuitry obtains granule protection information corresponding to a target granule of physical addresses including the target PA, which indicates at least one allowed PAS associated with the target granule, and blocks the memory access request when the granule protection information indicates that the selected PAS is not an allowed PAS.

公开(公告)号：US20250111576A1

公开(公告)日：2025-04-03

申请号：US18478666

申请日：2023-09-29

Applicant: Arm Limited

Inventor： Rafal Stepuch ,  Andreas Due Engh-Halstvedt ,  Frank Klaeboe Langtind

IPC: G06T15/00 ,  G06T15/04

Abstract: When preparing and storing primitive lists in a tile-based graphics processing system, one or more primitive list pointer arrays store pointers, each pointer indicating a location in storage of one or more of the primitive lists. A further pointer array stores further pointers, each further pointer indicating a location in storage of one or more of the primitive list pointer arrays.

公开(公告)号：US20250111540A1

公开(公告)日：2025-04-03

申请号：US18477090

申请日：2023-09-28

Applicant: Arm Limited

Inventor： Maxim NOVIKOV ,  Liam O'NEIL ,  Yanxiang WANG ,  Joshua James SOWERBY

IPC: G06T9/00 ,  G06T5/00 ,  G06T5/50 ,  G06T7/11

Abstract: A method and system for processing image data having a first bit depth using at least one trained neural network configured to operate on data having a second bit depth, where the second bit depth is smaller than the first bit depth by generating a plurality of image data portions by splitting the image data. Each of the plurality of image data portions is encoded to produce a plurality of encoded image data portions having the second bit depth. The plurality of image data portions are then processed by at least one trained neural network, before being decoded and combined to produce composite image data. The composite image data is then output.

公开(公告)号：US20250111465A1

公开(公告)日：2025-04-03

申请号：US18478657

申请日：2023-09-29

Applicant: Arm Limited

Inventor： Olof Henrik Uhrenholt ,  Thomas Weber

IPC: G06T1/20

Abstract: A method of managing write-after-read (WAR) hazards in a graphics processor. A host processor when preparing a graphics processor command stream can identify possible WAR hazards between rendering jobs for example by detecting layout transitions and insert a suitable barrier into the graphics processor command stream. The graphics processor when encountering such a barrier can then determine whether it is possible to ignore the barrier and allow rendering jobs to be processed concurrently.

公开(公告)号：US20250111463A1

公开(公告)日：2025-04-03

申请号：US18478121

申请日：2023-09-29

Applicant: Arm Limited

Inventor： Olof Henrik Uhrenholt ,  Andreas Due Engh-Halstvedt ,  Philip Carlos Garcia ,  Wing-Tsi Henry Wong ,  Sandeep Kala ,  Joseph Michael Richardson

IPC: G06T1/20

Abstract: When generating a sequence of render outputs using a graphics processor, the completion status of rendering tasks from different render outputs is tracked so that processing tasks for later render outputs in the sequence of outputs can be processed concurrently with processing tasks for earlier render outputs in the sequence of outputs whilst ensuring that any dependencies between the rendering tasks for the different render outputs are enforced.

公开(公告)号：US20250110863A1

公开(公告)日：2025-04-03

申请号：US18477625

申请日：2023-09-29

Applicant: Arm Limited

Inventor： . ABHISHEK RAJA

IPC: G06F12/02

Abstract: There is provided an apparatus, system, chip-containing product, method, and storage medium. The apparatus comprises memory access circuitry responsive to one or more types of memory access request, to retrieve specified data items from memory. The apparatus is also provided with local storage circuitry configured to store at least some of the retrieved data items. The local storage circuitry is N-way associative, and N is greater than 1. The apparatus is also provided with control circuitry responsive to an indication that an access request signalled to the local storage circuitry relating to an accessed data item corresponds to a predefined type of memory access request, to implement a restrictive access policy in relation to the accessed data item in the local storage circuitry. The restrictive access policy excludes at least one step of accessing an excluded subset of ways of the local storage circuitry.

公开(公告)号：US20250103681A1

公开(公告)日：2025-03-27

申请号：US18890214

申请日：2024-09-19

Applicant: Arm Limited

Inventor： Olof Henrik Uhrenholt

IPC: G06F17/17 ,  G06F1/03

Abstract: A processing element is configured to approximate a transcendental function. The processing element comprises an input storage and a look-up storage. The processing element obtains floating-point input data from the input storage representing having an input exponent value and an input mantissa value. The processing element looks up approximation parameters and an output exponent value from the look-up storage, wherein each group of approximation parameters and output exponent value are stored in the look-up storage in association with a respective range of a plurality of ranges that are defined by the input exponent value and the input mantissa value. The ranges cover values of the input exponent value and input mantissa value such that the output exponent value associated with each range does not change by more than a predetermined number. An approximation function is evaluated that approximates the transcendental function based on the looked-up approximation parameters and output exponent.

公开(公告)号：US12260218B2

公开(公告)日：2025-03-25

申请号：US18343294

申请日：2023-06-28

Applicant: Arm Limited

Inventor： Quentin Éric Nouvel ,  Luca Nassi ,  Nicola Piano ,  Albin Pierrick Tonnerre ,  Geoffray Matthieu Lacourba

IPC: G06F9/30 ,  G06F9/38

Abstract: There is provided an apparatus, method for data processing. The apparatus comprises post decode cracking circuitry responsive to receipt of decoded instructions from decode circuitry of a processing pipeline, to crack the decoded instructions into micro-operations to be processed by processing circuitry of the processing pipeline. The post decode cracking circuitry is responsive to receipt of a decoded instruction suitable for cracking into a plurality of micro-operations including at least one pair of micro-operations having a producer-consumer data dependency, to generate the plurality of micro-operations including a producer micro-operation and a consumer micro-operation, and to assign a transfer register to transfer data between the producer micro-operation and the consumer micro-operation.