公开(公告)号：US20090001465A1

公开(公告)日：2009-01-01

申请号：US11769912

申请日：2007-06-28

Applicant: Amanda L. Tessier ,  Bryant C. Colwill ,  Brian L. Tessier

Inventor： Amanda L. Tessier ,  Bryant C. Colwill ,  Brian L. Tessier

IPC: H01L27/01 ,  H01L21/4763

CPC classification number: H01L21/84 ,  H01L21/743 ,  H01L23/535 ,  H01L27/1203 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is provided of forming a conductive via in contact with a bulk semiconductor region of a semiconductor-on-insulator (“SOI”) substrate. A first opening is formed in a conformal layer overlying a trench isolation region. The trench isolation region may share an edge with an SOI layer of the substrate. Desirably, a dielectric layer is deposited over a top surface of the conformal layer and the trench isolation region. A second opening can then be formed which extends through the dielectric layer and the first opening in the conformal layer. Desirably, portions of the bulk semiconductor region and the top surface of the conformal layer are exposed within the second opening. The second opening can then be filled with at least one of a metal or a semiconductor to form a conductive element contacting the exposed portions of the bulk semiconductor region and the top surface of the conformal layer.

Abstract translation: 提供了一种形成与绝缘体上半导体（“SOI”）衬底的体半导体区域接触的导电通孔的方法。 在覆盖沟槽隔离区域的保形层中形成第一开口。 沟槽隔离区可以与衬底的SOI层共享边缘。 期望地，在保形层和沟槽隔离区的顶表面上沉积电介质层。 然后可以形成延伸穿过电介质层和保形层中的第一开口的第二开口。 理想的是，半导体区域的部分和保形层的顶表面在第二开口内露出。 然后可以用金属或半导体中的至少一个填充第二开口，以形成接触体半导体区域的暴露部分和保形层顶表面的导电元件。

公开(公告)号：US20080188014A1

公开(公告)日：2008-08-07

申请号：US11306717

申请日：2006-01-09

Applicant: Ricky S. Amos ,  Bryant C. Colwill ,  Kevin E. Mello

Inventor： Ricky S. Amos ,  Bryant C. Colwill ,  Kevin E. Mello

IPC: H01L21/66

CPC classification number: H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L22/12

Abstract: Embodiments herein present a method for a feed forward suicide control scheme based on spacer height controlling pre-clean time. The method forms field effect transistor gates over a substrate and then forms spacers on the gates. Next, the method measures the spacers using an atomic force microscope to determine a measured spacer height. The method then conducts a pre-cleaning etch, wherein a duration of the pre-cleaning is adjusted according to the measured spacer height. If the measured spacer height is below a predetermined amount, the duration of the pre-cleaning is reduced; and, if the measured spacer height is above a predetermined amount, the duration of the pre-cleaning is increased.

Abstract translation: 本文的实施方案提供了一种基于间隔物高度控制预清洁时间的前馈自杀控制方案。 该方法在衬底上形成场效应晶体管栅极，然后在栅极上形成间隔物。 接下来，该方法使用原子力显微镜测量间隔物以确定测量的间隔物高度。 然后，该方法进行预清洗蚀刻，其中根据测量的间隔物高度调节预清洁的持续时间。 如果测量的间隔物高度低于预定量，则预清洁的持续时间减少; 并且如果测量的间隔物高度高于预定量，则预清洁的持续时间增加。

公开(公告)号：US20100109119A1

公开(公告)日：2010-05-06

申请号：US12685690

申请日：2010-01-12

Applicant: Amanda L. Tessier ,  Bryant C. Colwill ,  Brian L. Tessier

Inventor： Amanda L. Tessier ,  Bryant C. Colwill ,  Brian L. Tessier

IPC: H01L27/12

CPC classification number: H01L21/84 ,  H01L21/743 ,  H01L23/535 ,  H01L27/1203 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a microelectronic structure including a conductive element contacting a bulk semiconductor region of a substrate, the bulk semiconductor region being separated from a semiconductor-on-insulator (“SOI”) layer of the substrate by a buried dielectric layer. The microelectronic structure includes a trench isolation region overlying the buried dielectric layer, the trench isolation region sharing an edge with the SOI layer; a conformal layer overlying the trench isolation region, the conformal layer having a top surface and an opening defining a wall extending from the top surface towards the trench isolation region, the top surface including a lip portion adjacent to the wall; a dielectric layer overlying the top surface of the conformal layer; and a conductive element in conductive communication with the bulk semiconductor region, the conductive element consisting essentially of at least one of a semiconductor, a metal, and a conductive compound of a metal, and extending through the dielectric layer, the opening in the conformal layer, the trench isolation region, and the buried dielectric layer, and the conductive element contacting the lip portion.

Abstract translation: 本发明的实施例提供一种微电子结构，其包括接触衬底的体半导体区域的导电元件，所述体半导体区域通过掩埋介电层与衬底的绝缘体上半导体（“SOI”）层分离。 微电子结构包括覆盖掩埋介质层的沟槽隔离区域，沟槽隔离区域与SOI层共享边缘; 覆盖所述沟槽隔离区域的共形层，所述共形层具有顶表面和限定从所述顶表面朝向所述沟槽隔离区域延伸的壁的开口，所述顶表面包括邻近所述壁的唇部; 覆盖保形层的顶表面的电介质层; 以及与体半导体区域导电连通的导电元件，所述导电元件基本上由金属的半导体，金属和导电化合物中的至少一种组成并且延伸穿过所述电介质层，所述共形层中的所述开口 沟槽隔离区和埋入介质层，导电元件与唇部接触。

公开(公告)号：US07718514B2

公开(公告)日：2010-05-18

申请号：US11769912

申请日：2007-06-28

Applicant: Amanda L. Tessier ,  Bryant C. Colwill ,  Brian L. Tessier

Inventor： Amanda L. Tessier ,  Bryant C. Colwill ,  Brian L. Tessier

IPC: H01L21/20

CPC classification number: H01L21/84 ,  H01L21/743 ,  H01L23/535 ,  H01L27/1203 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is provided of forming a conductive via in contact with a bulk semiconductor region of a semiconductor-on-insulator (“SOI”) substrate. A first opening is formed in a conformal layer overlying a trench isolation region. The trench isolation region may share an edge with an SOI layer of the substrate. Desirably, a dielectric layer is deposited over a top surface of the conformal layer and the trench isolation region. A second opening can then be formed which extends through the dielectric layer and the first opening in the conformal layer. Desirably, portions of the bulk semiconductor region and the top surface of the conformal layer are exposed within the second opening. The second opening can then be filled with at least one of a metal or a semiconductor to form a conductive element contacting the exposed portions of the bulk semiconductor region and the top surface of the conformal layer.

Abstract translation: 提供了一种形成与绝缘体上半导体（“SOI”）衬底的体半导体区域接触的导电通孔的方法。 在覆盖沟槽隔离区域的保形层中形成第一开口。 沟槽隔离区可以与衬底的SOI层共享边缘。 期望地，在保形层和沟槽隔离区的顶表面上沉积电介质层。 然后可以形成延伸穿过电介质层和保形层中的第一开口的第二开口。 理想的是，半导体区域的部分和保形层的顶表面在第二开口内露出。 然后可以用金属或半导体中的至少一个填充第二开口，以形成接触体半导体区域的暴露部分和保形层顶表面的导电元件。

公开(公告)号：US06797592B2

公开(公告)日：2004-09-28

申请号：US10421969

申请日：2003-04-23

Applicant: Jeffrey S. Brown ,  Bryant C. Colwill ,  Terence B. Hook ,  Dennis Hoyniak

Inventor： Jeffrey S. Brown ,  Bryant C. Colwill ,  Terence B. Hook ,  Dennis Hoyniak

IPC: H01L21265

CPC classification number: H01L21/823878 ,  H01L21/2652 ,  H01L21/266 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823892

Abstract: A method of ion implantation is provided. The method comprising: providing a substrate; forming a masking image having a sidewall on the substrate; forming a blocking layer on the substrate and on the masking image; and performing a retrograde ion implant through the blocking layer into the substrate, wherein the blocking layer substantially blocks ions scattered at the sidewall of the masking layer.

Abstract translation: 提供了离子注入的方法。 该方法包括：提供衬底; 在所述基板上形成具有侧壁的掩模图像; 在衬底和掩蔽图像上形成阻挡层; 以及通过所述阻挡层进行逆向离子注入到所述衬底中，其中所述阻挡层基本上阻挡在所述掩蔽层的侧壁处散射的离子。

公开(公告)号：US06610585B1

公开(公告)日：2003-08-26

申请号：US10083062

申请日：2002-02-26

Applicant: Jeffrey S. Brown ,  Bryant C. Colwill ,  Terence B. Hook ,  Dennis Hoyniak

Inventor： Jeffrey S. Brown ,  Bryant C. Colwill ,  Terence B. Hook ,  Dennis Hoyniak

IPC: H01L21265

CPC classification number: H01L21/823878 ,  H01L21/2652 ,  H01L21/266 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823892

Abstract: A method of ion implantation is provided. The method comprising: providing a substrate; forming a masking image having a sidewall on the substrate; forming a blocking layer on the substrate and on the masking image; and performing a retrograde ion implant through the blocking layer into the substrate, wherein the blocking layer substantially blocks ions scattered at the sidewall of the masking layer.

公开(公告)号：US07888738B2

公开(公告)日：2011-02-15

申请号：US12685690

申请日：2010-01-12

Applicant: Amanda L. Tessier ,  Brian L. Tessier ,  Bryant C. Colwill

Inventor： Amanda L. Tessier ,  Brian L. Tessier ,  Bryant C. Colwill

IPC: H01L27/12

CPC classification number: H01L21/84 ,  H01L21/743 ,  H01L23/535 ,  H01L27/1203 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a microelectronic structure including a conductive element contacting a bulk semiconductor region of a substrate, the bulk semiconductor region being separated from a semiconductor-on-insulator (“SOI”) layer of the substrate by a buried dielectric layer. The microelectronic structure includes a trench isolation region overlying the buried dielectric layer, the trench isolation region sharing an edge with the SOI layer; a conformal layer overlying the trench isolation region, the conformal layer having a top surface and an opening defining a wall extending from the top surface towards the trench isolation region, the top surface including a lip portion adjacent to the wall; a dielectric layer overlying the top surface of the conformal layer; and a conductive element in conductive communication with the bulk semiconductor region, the conductive element consisting essentially of at least one of a semiconductor, a metal, and a conductive compound of a metal, and extending through the dielectric layer, the opening in the conformal layer, the trench isolation region, and the buried dielectric layer, and the conductive element contacting the lip portion.

Abstract translation: 本发明的实施例提供一种微电子结构，其包括接触衬底的体半导体区域的导电元件，所述体半导体区域通过掩埋介电层与衬底的绝缘体上半导体（“SOI”）层分离。 微电子结构包括覆盖掩埋介质层的沟槽隔离区域，沟槽隔离区域与SOI层共享边缘; 覆盖所述沟槽隔离区域的共形层，所述共形层具有顶表面和限定从所述顶表面朝向所述沟槽隔离区域延伸的壁的开口，所述顶表面包括邻近所述壁的唇部; 覆盖保形层的顶表面的电介质层; 以及与体半导体区域导电连通的导电元件，所述导电元件基本上由金属的半导体，金属和导电化合物中的至少一种组成并且延伸穿过所述电介质层，所述共形层中的所述开口 沟槽隔离区和埋入介质层，导电元件与唇部接触。

公开(公告)号：US07479436B2

公开(公告)日：2009-01-20

申请号：US11306717

申请日：2006-01-09

Applicant: Ricky S. Amos ,  Bryant C. Colwill ,  Kevin E. Mello

Inventor： Ricky S. Amos ,  Bryant C. Colwill ,  Kevin E. Mello

IPC: H01L21/336

CPC classification number: H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L22/12

Abstract: Embodiments herein present a method for a feed forward silicide control scheme based on spacer height controlling pre-clean time. The method forms field effect transistor gates over a substrate and then forms spacers on the gates. Next, the method measures the spacers using an atomic force microscope to determine a measured spacer height. The method then conducts a pre-cleaning etch, wherein a duration of the pre-cleaning is adjusted according to the measured spacer height. If the measured spacer height is below a predetermined amount, the duration of the pre-cleaning is reduced; and, if the measured spacer height is above a predetermined amount, the duration of the pre-cleaning is increased.

Abstract translation: 本文的实施方案提供了基于间隔物高度控制预清洁时间的前馈硅化物控制方案的方法。 该方法在衬底上形成场效应晶体管栅极，然后在栅极上形成间隔物。 接下来，该方法使用原子力显微镜测量间隔物以确定测量的间隔物高度。 然后，该方法进行预清洗蚀刻，其中根据测量的间隔物高度调节预清洁的持续时间。 如果测量的间隔物高度低于预定量，则预清洁的持续时间减少; 并且如果测量的间隔物高度高于预定量，则预清洁的持续时间增加。