公开(公告)号：US07755713B2

公开(公告)日：2010-07-13

申请号：US12234700

申请日：2008-09-21

Applicant: Heng-Chang Lin ,  Yu-Fang Wang ,  Ming-Kang Huang ,  Chih-Kun Lin

Inventor： Heng-Chang Lin ,  Yu-Fang Wang ,  Ming-Kang Huang ,  Chih-Kun Lin

IPC: G02F1/1333 ,  G02F1/1345 ,  G01R31/00

CPC classification number: G02F1/13452 ,  G02F2001/136254

Abstract: A peripheral circuit disposed on a substrate having an active device array is provided. The peripheral circuit includes first test pads, second test pads, first lines, and second lines. The first and the second lines are electrically connected to the active device array. Each first test pad includes a first conductive layer and a second conductive layer electrically connected to the first conductive layer. The first conductive layer electrically connects at least two of the adjacent first lines. The second test pads are interposed between the first test pads and the active device array. Each second test pad includes third conductive layers and a fourth conductive layer electrically connected to the third conductive layers. The first lines pass through the third conductive layers and are insulated from the fourth conductive layer. Each third conductive layer is electrically connected to one of the adjacent second lines respectively.

Abstract translation: 设置在具有有源器件阵列的衬底上的外围电路。 外围电路包括第一测试焊盘，第二测试焊盘，第一线和第二线。 第一和第二线电连接到有源器件阵列。 每个第一测试焊盘包括电连接到第一导电层的第一导电层和第二导电层。 第一导电层电连接相邻第一线中的至少两个。 第二测试焊盘插入在第一测试焊盘和有源器件阵列之间。 每个第二测试焊盘包括第三导电层和与第三导电层电连接的第四导电层。 第一线穿过第三导电层并与第四导电层绝缘。 每个第三导电层分别电连接到相邻的第二线之一。

公开(公告)号：US08405416B2

公开(公告)日：2013-03-26

申请号：US12780886

申请日：2010-05-15

Applicant: Chun-lang Chiu ,  Ren-tsai Hung ,  Ming-kang Huang ,  Chih-kun Lin

Inventor： Chun-lang Chiu ,  Ren-tsai Hung ,  Ming-kang Huang ,  Chih-kun Lin

IPC: G01R31/02

CPC classification number: H05K3/4007 ,  G01R1/07314 ,  G01R3/00 ,  H05K3/0079 ,  H05K3/0082 ,  H05K2201/09736 ,  H05K2203/1476

Abstract: A probe includes a wire and a bump, wherein the wire is formed on a substrate; and the bump is formed upon the wire. In addition, a probe block includes a plurality of probes disposed on a substrate, so that the probe block is composed of a plurality of wires and bumps. The wires are disposed on the substrate and each bump is disposed accurately upon an end of each wire. The bump and the wire of the probe in accordance with the present invention are formed jointlessly. A method of fabricating the probe is characterized in that a grayscale mask is utilized to form the wire on the substrate and form the bump upon the wire by using a single masking process.

Abstract translation: 探针包括线和凸块，其中线形成在衬底上; 并且凸起形成在线上。 此外，探针块包括设置在基板上的多个探针，使得探针块由多个线和凸块组成。 电线设置在基板上，并且每个凸块精确地设置在每根导线的端部上。 根据本发明的探针的凸起和线被无接缝地形成。 制造探针的方法的特征在于，利用灰度掩模在衬底上形成线，并通过使用单一掩蔽工艺在线上形成凸块。

公开(公告)号：US20110210760A1

公开(公告)日：2011-09-01

申请号：US12780886

申请日：2010-05-15

Applicant: CHUN-LANG CHIU ,  Ren-tsai Hung ,  Ming-kang Huang ,  Chih-kun Lin

Inventor： CHUN-LANG CHIU ,  Ren-tsai Hung ,  Ming-kang Huang ,  Chih-kun Lin

IPC: G01R31/02 ,  H05K3/00 ,  G01R1/067

CPC classification number: H05K3/4007 ,  G01R1/07314 ,  G01R3/00 ,  H05K3/0079 ,  H05K3/0082 ,  H05K2201/09736 ,  H05K2203/1476

Abstract: A probe and a method fabricating the same are disclosed. The probe includes a wire and a bump, wherein the wire is formed on a substrate; and the bump is formed upon the wire. In addition, a probe block is disclosed. The probe block includes a plurality of probes disposed on a substrate, so that the probe block is composed of a plurality of wires and bumps. The wires are disposed on the substrate and each bump is disposed accurately upon an end of each wire. The bump and the wire of the probe in accordance with the present invention are formed jointlessly. The method of fabricating the probe is characterized in that a grayscale mask is utilized to form the wire on the substrate and form the bump upon the wire by using a single masking process.

Abstract translation: 公开了一种探针及其制造方法。 探针包括线和凸块，其中线形成在衬底上; 并且凸起形成在线上。 另外，公开了探针块。 探针块包括设置在基板上的多个探针，使得探针块由多个线和凸块组成。 电线设置在基板上，并且每个凸块精确地设置在每根导线的端部上。 根据本发明的探针的凸起和线被无接缝地形成。 制造探针的方法的特征在于，使用灰度掩模在衬底上形成线，并通过使用单一掩蔽工艺在线上形成凸块。

公开(公告)号：US20090207369A1

公开(公告)日：2009-08-20

申请号：US12234700

申请日：2008-09-21

Applicant: Heng-Chang Lin ,  Yu-Fang Wang ,  Ming-Kang Huang ,  Chih-Kun Lin

Inventor： Heng-Chang Lin ,  Yu-Fang Wang ,  Ming-Kang Huang ,  Chih-Kun Lin

IPC: G02F1/1345

CPC classification number: G02F1/13452 ,  G02F2001/136254

Abstract: A peripheral circuit disposed on a substrate having an active device array is provided. The peripheral circuit includes first test pads, second test pads, first lines, and second lines. The first and the second lines are electrically connected to the active device array. Each first test pad includes a first conductive layer and a second conductive layer electrically connected to the first conductive layer. The first conductive layer electrically connects at least two of the adjacent first lines. The second test pads are interposed between the first test pads and the active device array. Each second test pad includes third conductive layers and a fourth conductive layer electrically connected to the third conductive layers. The first lines pass through the third conductive layers and are insulated from the fourth conductive layer. Each third conductive layer is electrically connected to one of the adjacent second lines respectively.

Abstract translation: 设置在具有有源器件阵列的衬底上的外围电路。 外围电路包括第一测试焊盘，第二测试焊盘，第一线和第二线。 第一和第二线电连接到有源器件阵列。 每个第一测试焊盘包括电连接到第一导电层的第一导电层和第二导电层。 第一导电层电连接相邻第一线中的至少两个。 第二测试焊盘插入在第一测试焊盘和有源器件阵列之间。 每个第二测试焊盘包括第三导电层和与第三导电层电连接的第四导电层。 第一线穿过第三导电层并与第四导电层绝缘。 每个第三导电层分别电连接到相邻的第二线之一。