公开(公告)号：US20100227442A1

公开(公告)日：2010-09-09

申请号：US12544231

申请日：2009-08-20

Applicant: Ya-Ju Lu ,  Jun-Yao Huang ,  Ming-Chu Chen ,  Yu-Fang Wang ,  Chun-Jen Ma

Inventor： Ya-Ju Lu ,  Jun-Yao Huang ,  Ming-Chu Chen ,  Yu-Fang Wang ,  Chun-Jen Ma

IPC: H01L21/336

CPC classification number: H01L29/66765 ,  H01L27/1255 ,  H01L27/1288

Abstract: A method of manufacturing thin film transistor is provided, in which the method of manufacturing includes a new etching process of island semiconductor. The new etching process of island semiconductor is controlled by a flow rate of etching gas and a regulation of etching power. When etching the island semiconductor, a part of gate insulation layer exposed out of the island semiconductor is etched at the same time. Consequently, the thickness of gate insulation layer over the storage capacitance electrode is reduced, the distance between the pixel electrode and the storage capacitance electrode is decreased, and the storage capacitance of pixel is increased. Finally, the width of storage capacitance electrode is reduced appropriately and the aperture ratio of product is increased.

Abstract translation: 提供一种制造薄膜晶体管的方法，其中制造方法包括岛状半导体的新的蚀刻工艺。 岛状半导体的新的蚀刻工艺由蚀刻气体的流量和蚀刻功率的调节来控制。 当蚀刻岛状半导体时，同时蚀刻露出岛状半导体的栅极绝缘层的一部分。 因此，存储电容电极上的栅极绝缘层的厚度减小，像素电极和辅助电容电极之间的距离减小，并且像素的存储电容增加。 最后，适当降低了存储电容电极的宽度，增加了产品的开口率。

公开(公告)号：US20100104956A1

公开(公告)日：2010-04-29

申请号：US12339076

申请日：2008-12-19

Applicant: Te-Yu Chen ,  Chin-Lung Yeh ,  Yu-Fang Wang

Inventor： Te-Yu Chen ,  Chin-Lung Yeh ,  Yu-Fang Wang

IPC: G03F1/00

CPC classification number: G03F1/50

Abstract: A manufacturing method of asymmetric bumps is provided. First, a substrate is provided. A film layer is then formed on the substrate. Next, a complex photomask including at least one transparent region, a number of opaque regions, and a number of semi-transparent regions is provided. Each of the semi-transparent regions is disposed between two adjacent opaque regions, and at least one light-shielding pattern is randomly disposed in each of the semi-transparent regions. The film layer is then patterned with use of the complex photomask, and multiple asymmetric bumps are formed on the substrate. By using the complex photomask, manufacturing steps of the asymmetric bumps can be reduced. Besides, a manufacturing method of a pixel structure having the above-mentioned asymmetric bumps is also provided.

Abstract translation: 提供了一种不对称凸块的制造方法。 首先，提供基板。 然后在基板上形成膜层。 接下来，提供包括至少一个透明区域，多个不透明区域和多个半透明区域的复合光掩模。 每个半透明区域设置在两个相邻的不透明区域之间，并且至少一个遮光图案被随机地布置在每个半透明区域中。 然后使用复合光掩模对膜层进行构图，并且在衬底上形成多个不对称凸起。 通过使用复合光掩模，可以减少不对称凸块的制造步骤。 此外，还提供了具有上述不对称凸块的像素结构的制造方法。

公开(公告)号：US20060033863A1

公开(公告)日：2006-02-16

申请号：US11256801

申请日：2005-10-24

Applicant: Chih-Chieh Lan ,  Hung-Yi Hung ,  Yu-Fang Wang

Inventor： Chih-Chieh Lan ,  Hung-Yi Hung ,  Yu-Fang Wang

IPC: G02F1/1333

CPC classification number: G02F1/13394 ,  G02F1/136209

Abstract: A color liquid crystal display includes a control circuit located on a first transparent substrate. The control circuit includes control devices and a chessboard-like circuit with supporting areas. A passivation layer is located on the control circuit and has contact windows to expose electrodes of the control devices. A color filter layer is located on the passivation layer and pixel electrodes are located on the color filter layer. The pixel electrodes are electrically connected to the electrodes of the control devices through the contact windows. First photoresist layers are located on the supporting areas and the control devices, and second photoresist layers are located on the first photoresist layers. A common electrode is located on a surface of a second transparent substrate that faces the first transparent substrate. A liquid crystal layer is located between the first and the second transparent substrates.

Abstract translation: 彩色液晶显示器包括位于第一透明基板上的控制电路。 控制电路包括控制装置和具有支撑区域的棋盘状电路。 钝化层位于控制电路上，并具有接触窗口以暴露控制装置的电极。 滤色器层位于钝化层上，像素电极位于滤色器层上。 像素电极通过接触窗电连接到控制装置的电极。 第一光致抗蚀剂层位于支撑区域上，控制装置和第二光致抗蚀剂层位于第一光致抗蚀剂层上。 公共电极位于与第一透明基板相对的第二透明基板的表面上。 液晶层位于第一和第二透明基板之间。

公开(公告)号：US07999902B2

公开(公告)日：2011-08-16

申请号：US12353947

申请日：2009-01-14

Applicant: Te-Yu Chen ,  Chin-Lung Yeh ,  Yu-Fang Wang

Inventor： Te-Yu Chen ,  Chin-Lung Yeh ,  Yu-Fang Wang

IPC: G02F1/1345

CPC classification number: G02F1/1339 ,  G02F1/1345 ,  G02F2001/13415

Abstract: A liquid crystal display panel includes a first transparent substrate, a second transparent substrate opposite to the first transparent substrate, and a sealant disposed therebetween. The first transparent substrate includes a peripheral region, and a plurality of conductive lines disposed in the peripheral region. The conductive lines include a plurality of transparent conductive lines and non-transparent conductive lines. The sealant is disposed in the peripheral region.

Abstract translation: 液晶显示面板包括第一透明基板，与第一透明基板相对的第二透明基板和设置在其间的密封剂。 第一透明基板包括周边区域和设置在周边区域中的多条导线。 导线包括多个透明导电线和不透明导电线。 密封剂设置在周边区域中。

公开(公告)号：US07816194B2

公开(公告)日：2010-10-19

申请号：US12544231

申请日：2009-08-20

Applicant: Ya-Ju Lu ,  Jun-Yao Huang ,  Ming-Chu Chen ,  Yu-Fang Wang ,  Chun-Jen Ma

Inventor： Ya-Ju Lu ,  Jun-Yao Huang ,  Ming-Chu Chen ,  Yu-Fang Wang ,  Chun-Jen Ma

IPC: H01L21/84

CPC classification number: H01L29/66765 ,  H01L27/1255 ,  H01L27/1288

Abstract: A method of manufacturing thin film transistor is provided, in which the method of manufacturing includes a new etching process of island semiconductor. The new etching process of island semiconductor is controlled by a flow rate of etching gas and a regulation of etching power. When etching the island semiconductor, a part of gate insulation layer exposed out of the island semiconductor is etched at the same time. Consequently, the thickness of gate insulation layer over the storage capacitance electrode is reduced, the distance between the pixel electrode and the storage capacitance electrode is decreased, and the storage capacitance of pixel is increased. Finally, the width of storage capacitance electrode is reduced appropriately and the aperture ratio of product is increased.

Abstract translation: 提供一种制造薄膜晶体管的方法，其中制造方法包括岛状半导体的新的蚀刻工艺。 岛状半导体的新的蚀刻工艺由蚀刻气体的流量和蚀刻功率的调节来控制。 当蚀刻岛状半导体时，同时蚀刻露出岛状半导体的栅极绝缘层的一部分。 因此，存储电容电极上的栅极绝缘层的厚度减小，像素电极和辅助电容电极之间的距离减小，并且像素的存储电容增加。 最后，适当降低了存储电容电极的宽度，增加了产品的开口率。

公开(公告)号：US07755713B2

公开(公告)日：2010-07-13

申请号：US12234700

申请日：2008-09-21

Applicant: Heng-Chang Lin ,  Yu-Fang Wang ,  Ming-Kang Huang ,  Chih-Kun Lin

Inventor： Heng-Chang Lin ,  Yu-Fang Wang ,  Ming-Kang Huang ,  Chih-Kun Lin

IPC: G02F1/1333 ,  G02F1/1345 ,  G01R31/00

CPC classification number: G02F1/13452 ,  G02F2001/136254

Abstract: A peripheral circuit disposed on a substrate having an active device array is provided. The peripheral circuit includes first test pads, second test pads, first lines, and second lines. The first and the second lines are electrically connected to the active device array. Each first test pad includes a first conductive layer and a second conductive layer electrically connected to the first conductive layer. The first conductive layer electrically connects at least two of the adjacent first lines. The second test pads are interposed between the first test pads and the active device array. Each second test pad includes third conductive layers and a fourth conductive layer electrically connected to the third conductive layers. The first lines pass through the third conductive layers and are insulated from the fourth conductive layer. Each third conductive layer is electrically connected to one of the adjacent second lines respectively.

Abstract translation: 设置在具有有源器件阵列的衬底上的外围电路。 外围电路包括第一测试焊盘，第二测试焊盘，第一线和第二线。 第一和第二线电连接到有源器件阵列。 每个第一测试焊盘包括电连接到第一导电层的第一导电层和第二导电层。 第一导电层电连接相邻第一线中的至少两个。 第二测试焊盘插入在第一测试焊盘和有源器件阵列之间。 每个第二测试焊盘包括第三导电层和与第三导电层电连接的第四导电层。 第一线穿过第三导电层并与第四导电层绝缘。 每个第三导电层分别电连接到相邻的第二线之一。

公开(公告)号：US07746443B2

公开(公告)日：2010-06-29

申请号：US11257240

申请日：2005-10-24

Applicant: Chih-Chieh Lan ,  Hung-Yi Hung ,  Yu-Fang Wang

Inventor： Chih-Chieh Lan ,  Hung-Yi Hung ,  Yu-Fang Wang

IPC: G02F1/13 ,  G02F1/136 ,  G02F1/1335 ,  G02F1/1339

CPC classification number: G02F1/13394 ,  G02F1/136209

Abstract: A method of utilizing dual-layer photoresist to form black matrixes and spacers on a control circuit substrate is provided. The dual-layer photoresist includes a layer of black resin and a layer of transparent photoresist. The black resin, having an optical density greater than three, is mainly used to achieve the effect of black matrix. The transparent photoresist is mainly used to satisfy the needed cell gap between two transparent substrates.

Abstract translation: 提供了一种利用双层光致抗蚀剂在控制电路基板上形成黑矩阵和间隔物的方法。 双层光致抗蚀剂包括黑色树脂层和透明光致抗蚀剂层。 光密度大于3的黑色树脂主要用于实现黑色矩阵的效果。 透明光致抗蚀剂主要用于满足两个透明基板之间所需的单元间隙。

公开(公告)号：US08007987B2

公开(公告)日：2011-08-30

申请号：US12339076

申请日：2008-12-19

Applicant: Te-Yu Chen ,  Chin-Lung Yeh ,  Yu-Fang Wang

Inventor： Te-Yu Chen ,  Chin-Lung Yeh ,  Yu-Fang Wang

IPC: G03F7/20

CPC classification number: G03F1/50

Abstract: A manufacturing method of asymmetric bumps is provided. First, a substrate is provided. A film layer is then formed on the substrate. Next, a complex photomask including at least one transparent region, a number of opaque regions, and a number of semi-transparent regions is provided. Each of the semi-transparent regions is disposed between two adjacent opaque regions, and at least one light-shielding pattern is randomly disposed in each of the semi-transparent regions. The film layer is then patterned with use of the complex photomask, and multiple asymmetric bumps are formed on the substrate. By using the complex photomask, manufacturing steps of the asymmetric bumps can be reduced. Besides, a manufacturing method of a pixel structure having the above-mentioned asymmetric bumps is also provided.

Abstract translation: 提供了一种不对称凸块的制造方法。 首先，提供基板。 然后在基板上形成膜层。 接下来，提供包括至少一个透明区域，多个不透明区域和多个半透明区域的复合光掩模。 每个半透明区域设置在两个相邻的不透明区域之间，并且至少一个遮光图案被随机地布置在每个半透明区域中。 然后使用复合光掩模对膜层进行构图，并且在衬底上形成多个不对称凸起。 通过使用复合光掩模，可以减少不对称凸块的制造步骤。 此外，还提供了具有上述不对称凸块的像素结构的制造方法。

公开(公告)号：US06749975B2

公开(公告)日：2004-06-15

申请号：US10430750

申请日：2003-05-06

Applicant: Jia-Shyong Cheng ,  Yu-Fang Wang

Inventor： Jia-Shyong Cheng ,  Yu-Fang Wang

IPC: G02B520

CPC classification number: G02F1/13394 ,  G02F1/136209

Abstract: A method of utilizing color photoresist to form black matrix and spacers on a control circuit substrate is described. Utilizing the character of the red and the blue photoresist having a non-overlapping transmittance region in the visible light region, a black matrixes consisting of overlapping red and blue photoresist on control devices are used to prevent the photo current occurring in the off state of the control devices. In addition, three different color photoresist plus another-color photoresist are overlapped to form spacers on metal lines.

Abstract translation: 描述了利用彩色光致抗蚀剂在控制电路基板上形成黑矩阵和间隔物的方法。 利用在可见光区域具有不重叠的透射区域的红色和蓝色光致抗蚀剂的特征，使用由控制装置上的重叠的红色和蓝色光致抗蚀剂组成的黑色矩阵，以防止发生在关闭状态的光电流 控制装置。 另外，三种不同颜色的光致抗蚀剂加上另一种彩色光致抗蚀剂被重叠以在金属线上形成间隔物。

公开(公告)号：US06558971B2

公开(公告)日：2003-05-06

申请号：US09930789

申请日：2001-08-15

Applicant: In-Cha Hsieh ,  Yu-Fang Wang

Inventor： In-Cha Hsieh ,  Yu-Fang Wang

IPC: H01L2100

CPC classification number: G02F1/13458 ,  G02F1/1362

Abstract: A method for manufacturing an LCD panel comprises the steps of providing a substrate having a conducting layer forming a pad and a conducting line, and an isolation layer on the pad and the conducting line, forming a planarization layer on the isolation layer above the conducting line, and a first through hole in the planarization layer, the first through hole exposing the isolation layer and aligned with the conducting line, forming a masking layer on the isolation layer above the pad, and a second through hole in the masking layer, the second through hole exposing the isolation layer and aligned with the pad, and etching the isolation layer with the masking of the planarization layer and the masking layer, whereby the isolation layer exposed by the first and second through hole is removed.