Vibration damper
    1.
    发明授权
    Vibration damper 有权
    减振器

    公开(公告)号:US08322990B2

    公开(公告)日:2012-12-04

    申请号:US12458241

    申请日:2009-07-06

    IPC分类号: F01D25/04

    摘要: A vibration damper (28) is disclosed for use in a turbomachine, the turbomachine comprising at least one turbine rotor (19) having a plurality of radially extending blades (16, 17). Each blade has an aerofoil (22), a platform (21) and a stem (20). The vibration damper (28) has a seal-region (29) which comprises a pair of sealing surfaces (24, 25) configured for engagement with respective contact surfaces (24, 25) provided on adjacent blade platforms (21). The vibration damper (28) also has a mass-region (30) which is configured to extend radially inwardly from the seal-region (29) and to terminate at a position located between adjacent blade stems (20) (FIG. 4).

    摘要翻译: 公开了一种用于涡轮机中的振动阻尼器(28),所述涡轮机包括具有多个径向延伸的叶片(16,17)的至少一个涡轮机转子(19)。 每个叶片具有机翼(22),平台(21)和杆(20)。 减震器(28)具有一个密封区域(29),该密封区域包括一对密封表面(24,25),该密封表面被构造用于与设置在相邻的刀片平台(21)上的各个接触表面(24,25)接合。 振动阻尼器(28)还具有构造成从密封区域(29)径向向内延伸并终止于相邻叶片杆(20)(图4)之间的位置处的质量区域(30)。

    Vibration damper
    2.
    发明申请
    Vibration damper 有权
    减振器

    公开(公告)号:US20100028135A1

    公开(公告)日:2010-02-04

    申请号:US12458241

    申请日:2009-07-06

    IPC分类号: F01D25/06

    摘要: A vibration damper (28) is disclosed for use in a turbomachine, the turbomachine comprising at least one turbine rotor (19) having a plurality of radially extending blades (16, 17). Each blade has an aerofoil (22), a platform (21) and a stem (20). The vibration damper (28) has a seal-region (29) which comprises a pair of sealing surfaces (24, 25) configured for engagement with respective contact surfaces (24, 25) provided on adjacent blade platforms (21). The vibration damper (28) also has a mass-region (30) which is configured to extend radially inwardly from the seal-region (29) and to terminate at a position located between adjacent blade stems (20) (FIG. 4).

    摘要翻译: 公开了一种用于涡轮机中的振动阻尼器(28),所述涡轮机包括具有多个径向延伸的叶片(16,17)的至少一个涡轮机转子(19)。 每个叶片具有机翼(22),平台(21)和杆(20)。 减震器(28)具有一个密封区域(29),该密封区域包括一对密封表面(24,25),该密封表面被构造用于与设置在相邻的刀片平台(21)上的各个接触表面(24,25)接合。 振动阻尼器(28)还具有构造成从密封区域(29)径向向内延伸并终止于相邻叶片杆(20)(图4)之间的位置处的质量区域(30)。

    Array processor
    3.
    发明授权
    Array processor 失效
    阵列处理器

    公开(公告)号:US4467422A

    公开(公告)日:1984-08-21

    申请号:US508175

    申请日:1983-06-27

    申请人: David J. Hunt

    发明人: David J. Hunt

    摘要: An array processor in which each sub-array of processing elements has a group of check-bit processing elements associated with it. The check-code processing elements have north-south interconnections, but have no east-west connections. Instead, the northernmost element of each group is connected diagonally to the southernmost element of the neighboring group, so as to permit serial transfer of check codes, over the north-south connections and the diagonal connections, between adjacent groups in the east-west direction.

    摘要翻译: 一种阵列处理器,其中处理元件的每个子阵列具有与其相关联的一组校验位处理元件。 校验码处理元件具有南北互连,但没有东西连接。 相反,每个组的最北部元素与邻近组的最南端元素对角连接,以便允许在东西方向上的相邻组之间的南北连接和对角线连接的连续传输校验码 。

    Data processing system with error checking
    4.
    发明授权
    Data processing system with error checking 失效
    数据处理系统进行错误检查

    公开(公告)号:US4304002A

    公开(公告)日:1981-12-01

    申请号:US91552

    申请日:1979-11-05

    申请人: David J. Hunt

    发明人: David J. Hunt

    IPC分类号: G06F11/10 G06F15/80 G06F15/16

    CPC分类号: G06F11/10 G06F15/8023

    摘要: A data processing system is disclosed consisting of a plurality of data processing elements and parity processing elements. The parity processing elements hold parity bits for checking the contents of the internal registers and internal stores of the data processing elements and perform substantially the same operations on the parity bits as the data processing elements perform on the data. However, some of these operations may invalidate the parity bits. In particular, the carry result from an addition operation is not always valid. A parity valid logic circuit is therefore provided to generate a signal which indicates whether the parity bits from all the parity processing elements are valid, and hence whether the parity check performed using these parity bits is valid.

    摘要翻译: 公开了一种由多个数据处理元件和奇偶校验处理元件组成的数据处理系统。 奇偶校验处理元件保存用于检查数据处理元件的内部寄存器和内部存储器的内容的奇偶校验位,并且对数据处理元件对数据执行的奇偶校验位执行基本相同的操作。 然而,这些操作中的一些可能使奇偶校验位无效。 具体来说,加法运算的进位结果并不总是有效。 因此,提供奇偶校验有效逻辑电路以产生指示来自所有奇偶校验处理元件的奇偶校验位是否有效的信号,以及因此使用这些奇偶校验位执行的奇偶校验是否有效。

    Array processor
    5.
    发明授权
    Array processor 失效
    阵列处理器

    公开(公告)号:US4270169A

    公开(公告)日:1981-05-26

    申请号:US20802

    申请日:1979-03-15

    CPC分类号: G06F15/8023

    摘要: An array processor is described consisting of a plurality of modules connected together in rows and columns. Each module has at least one special terminal which, as well as providing a connection for transfer of data between adjacent modules, also provides an output which is combined with similar signals from the other modules in the same row, to form a row response signal. Alternate modules in each row are rotated by 180.degree. with respect to each other, so that the special terminals on adjacent modules are connected in pairs. This reduces the complexity of the circuits for forming the row response signals.

    摘要翻译: 描述了阵列处理器,其由以行和列连接在一起的多个模块组成。 每个模块具有至少一个专用终端,以及提供用于相邻模块之间的数据传输的连接,还提供与来自同一行中的其他模块的类似信号组合的输出,以形成行响应信号。 每行中的交替模块相对于彼此旋转180°,使得相邻模块上的特殊端子成对连接。 这降低了用于形成行响应信号的电路的复杂性。

    Vibration damper assembly
    6.
    发明授权
    Vibration damper assembly 有权
    振动阻尼器总成

    公开(公告)号:US08231352B2

    公开(公告)日:2012-07-31

    申请号:US12149493

    申请日:2008-05-02

    IPC分类号: F01D5/10

    CPC分类号: F01D5/22 Y10S416/50

    摘要: A vibration damper assembly for damping non-synchronous vibration between adjacent, spaced apart components comprises a vibration damper located in both of a pair of generally confronting passages in each of the components. The assembly comprises at least two spaced apart articulation surfaces for contact between damper and component, each of the articulation surfaces is arcuate in a first direction and is characterized by having a substantially linear portion in an orthogonal and second direction. Thereby the contact area is greatly enlarged and material loss minimized. The cross-sectional shape of the damper or passage is non-circular and there is a clearance between the damper and passage sufficiently small to prevent rotation of the damper in the passage during use.

    摘要翻译: 用于阻尼相邻隔开部件之间的非同步振动的振动阻尼器组件包括位于每个部件中的一对通常面对的通道中的振动阻尼器。 组件包括至少两个间隔开的关节表面,用于在阻尼器和部件之间接触,每个铰接表面在第一方向上呈弧形,并且其特征在于在正交和第二方向上具有基本上线性的部分。 因此,接触面积大大增加,材料损失最小化。 阻尼器或通道的横截面形状是非圆形的,并且阻尼器和通道之间的间隙足够小以防止在使用过程中阻尼器在通道中的旋转。

    Processor elements having multi-byte structure shift register for
shifting data either byte wise or bit wise with single-bit output
formed at bit positions thereof spaced by one byte
    7.
    发明授权
    Processor elements having multi-byte structure shift register for shifting data either byte wise or bit wise with single-bit output formed at bit positions thereof spaced by one byte 失效
    具有多字节结构移位寄存器的处理器元件用于以单位或位方式移位数据,其中单位输出形成在其位置间隔一个字节

    公开(公告)号:US5287532A

    公开(公告)日:1994-02-15

    申请号:US613217

    申请日:1990-11-14

    申请人: David J. Hunt

    发明人: David J. Hunt

    IPC分类号: G06F15/16 G06F15/80

    CPC分类号: G06F15/8023

    摘要: A processor array (2) employs an SIMD architecture and includes a number of single-bit processor elements. Each processor element includes an arithmetic unit (ALU) and at least one operand register (Q) for the arithmetic unit (ALU). Each processor element (PE) further includes a multi-byte bit-wise shift register. Data outputs are formed in said shift register for each byte position. Data is communicated from a selected one of the outputs to the arithmetic unit via a multiplexer (Z-MUX).In one example, the shift register is unidirectional and includes a cyclical data path which connects the least significant bit of the register to the most significant end. The register may output data from one of the outputs and shift data cyclically from the most significant to the least significant end in a single operation.

    摘要翻译: 处理器阵列(2)采用SIMD架构并且包括多个单位处理器元件。 每个处理器元件包括算术单元(ALU)和用于算术单元(ALU)的至少一个操作数寄存器(Q)。 每个处理器元件(PE)还包括多字节逐位移位寄存器。 数据输出形成在每个字节位置的所述移位寄存器中。 通过多路复用器(Z-MUX)将数据从选定的一个输出传送到算术单元。 在一个示例中,移位寄存器是单向的,并且包括将寄存器的最低有效位连接到最高有效端的循环数据路径。 寄存器可以在单个操作中从一个输出端输出数据,并将数据从最高有效位置循环移位到最低有效端。

    Binary adder with shifting function
    8.
    发明授权
    Binary adder with shifting function 失效
    具有移位功能的二进制加法器

    公开(公告)号:US4241413A

    公开(公告)日:1980-12-23

    申请号:US20913

    申请日:1979-03-15

    申请人: David J. Hunt

    发明人: David J. Hunt

    CPC分类号: G06F7/50

    摘要: A binary adder has a switching circuit connected to one of its inputs. When activated by a mode selection signal, the switching circuit forces two of the adder inputs to receive the same input signal. In this condition the adder acts effectively as a connector, coupling two of its inputs direct to the sum and carry outputs. The invention is useful in an array processor, for performing additions and shifting operations.

    摘要翻译: 二进制加法器具有连接到其输入之一的开关电路。 当通过模式选择信号激活时,开关电路迫使两个加法器输入端接收相同的输入信号。 在这种情况下,加法器有效地作为连接器,将其两个输入直接耦合到和并传送输出。 本发明在阵列处理器中有用,用于执行添加和移位操作。

    Processor array system incorporating n-bit scalar processor and m x
m-bit processor array
    9.
    发明授权
    Processor array system incorporating n-bit scalar processor and m x m-bit processor array 失效
    加工N位标尺处理器和M X M位处理器阵列的处理器阵列系统

    公开(公告)号:US5150290A

    公开(公告)日:1992-09-22

    申请号:US397709

    申请日:1989-08-23

    申请人: David J. Hunt

    发明人: David J. Hunt

    CPC分类号: G06F15/8023

    摘要: A processor array system includes an n-bit scalar processor (2) and an m x m-bit processor array (1), m and n being integers, with m greater than n. The system also includes an array support circuit (3) which is connected between the scalar processor (2) and the processor array (1) and communicates data between them. The system may include an n-bit wide data path linking n-bit scalar processor registers in the scalar processor to the array support circuit (3) together with an m-bit wide data path linking the array support circuit (3) to the processor array (1). The array support circuit (3) includes a register interface arranged to interface the n-bit scalar processor registers to the processor array (1). The array support circuit (3) also includes an m-bit wide edge registers (ME) which is connected to the processor array (1) via the m-bit wide data path. The array may employ an SIMD architecture with each of a number of single bit processing elements having associated with it local store.

    Vibration damper assembly
    10.
    发明申请
    Vibration damper assembly 有权
    振动阻尼器总成

    公开(公告)号:US20100034657A1

    公开(公告)日:2010-02-11

    申请号:US12149493

    申请日:2008-05-02

    IPC分类号: F01D5/26

    CPC分类号: F01D5/22 Y10S416/50

    摘要: A vibration damper assembly for damping non-synchronous vibration between adjacent, spaced apart components comprises a vibration damper located in both of a pair of generally confronting passages in each of the components. The assembly comprises at least two spaced apart articulation surfaces for contact between damper and component, each of the articulation surfaces is arcuate in a first direction and is characterised by having a substantially linear portion in an orthogonal and second direction. Thereby the contact area is greatly enlarged and material loss minimised. The cross-sectional shape of the damper or passage is non-circular and there is a clearance between the damper and passage sufficiently small to prevent rotation of the damper in the passage during use.

    摘要翻译: 用于阻尼相邻隔开部件之间的非同步振动的振动阻尼器组件包括位于每个部件中的一对通常面对的通道中的振动阻尼器。 组件包括至少两个间隔开的关节表面,用于在阻尼器和部件之间接触,每个铰接表面在第一方向上呈弧形,并且其特征在于在正交和第二方向上具有基本上线性的部分。 因此,接触面积大大增加,材料损失最小化。 阻尼器或通道的横截面形状是非圆形的,并且阻尼器和通道之间的间隙足够小以防止在使用过程中阻尼器在通道中的旋转。