摘要:
A vibration damper (28) is disclosed for use in a turbomachine, the turbomachine comprising at least one turbine rotor (19) having a plurality of radially extending blades (16, 17). Each blade has an aerofoil (22), a platform (21) and a stem (20). The vibration damper (28) has a seal-region (29) which comprises a pair of sealing surfaces (24, 25) configured for engagement with respective contact surfaces (24, 25) provided on adjacent blade platforms (21). The vibration damper (28) also has a mass-region (30) which is configured to extend radially inwardly from the seal-region (29) and to terminate at a position located between adjacent blade stems (20) (FIG. 4).
摘要:
A vibration damper (28) is disclosed for use in a turbomachine, the turbomachine comprising at least one turbine rotor (19) having a plurality of radially extending blades (16, 17). Each blade has an aerofoil (22), a platform (21) and a stem (20). The vibration damper (28) has a seal-region (29) which comprises a pair of sealing surfaces (24, 25) configured for engagement with respective contact surfaces (24, 25) provided on adjacent blade platforms (21). The vibration damper (28) also has a mass-region (30) which is configured to extend radially inwardly from the seal-region (29) and to terminate at a position located between adjacent blade stems (20) (FIG. 4).
摘要:
An array processor in which each sub-array of processing elements has a group of check-bit processing elements associated with it. The check-code processing elements have north-south interconnections, but have no east-west connections. Instead, the northernmost element of each group is connected diagonally to the southernmost element of the neighboring group, so as to permit serial transfer of check codes, over the north-south connections and the diagonal connections, between adjacent groups in the east-west direction.
摘要:
A data processing system is disclosed consisting of a plurality of data processing elements and parity processing elements. The parity processing elements hold parity bits for checking the contents of the internal registers and internal stores of the data processing elements and perform substantially the same operations on the parity bits as the data processing elements perform on the data. However, some of these operations may invalidate the parity bits. In particular, the carry result from an addition operation is not always valid. A parity valid logic circuit is therefore provided to generate a signal which indicates whether the parity bits from all the parity processing elements are valid, and hence whether the parity check performed using these parity bits is valid.
摘要:
An array processor is described consisting of a plurality of modules connected together in rows and columns. Each module has at least one special terminal which, as well as providing a connection for transfer of data between adjacent modules, also provides an output which is combined with similar signals from the other modules in the same row, to form a row response signal. Alternate modules in each row are rotated by 180.degree. with respect to each other, so that the special terminals on adjacent modules are connected in pairs. This reduces the complexity of the circuits for forming the row response signals.
摘要:
A vibration damper assembly for damping non-synchronous vibration between adjacent, spaced apart components comprises a vibration damper located in both of a pair of generally confronting passages in each of the components. The assembly comprises at least two spaced apart articulation surfaces for contact between damper and component, each of the articulation surfaces is arcuate in a first direction and is characterized by having a substantially linear portion in an orthogonal and second direction. Thereby the contact area is greatly enlarged and material loss minimized. The cross-sectional shape of the damper or passage is non-circular and there is a clearance between the damper and passage sufficiently small to prevent rotation of the damper in the passage during use.
摘要:
A processor array (2) employs an SIMD architecture and includes a number of single-bit processor elements. Each processor element includes an arithmetic unit (ALU) and at least one operand register (Q) for the arithmetic unit (ALU). Each processor element (PE) further includes a multi-byte bit-wise shift register. Data outputs are formed in said shift register for each byte position. Data is communicated from a selected one of the outputs to the arithmetic unit via a multiplexer (Z-MUX).In one example, the shift register is unidirectional and includes a cyclical data path which connects the least significant bit of the register to the most significant end. The register may output data from one of the outputs and shift data cyclically from the most significant to the least significant end in a single operation.
摘要:
A binary adder has a switching circuit connected to one of its inputs. When activated by a mode selection signal, the switching circuit forces two of the adder inputs to receive the same input signal. In this condition the adder acts effectively as a connector, coupling two of its inputs direct to the sum and carry outputs. The invention is useful in an array processor, for performing additions and shifting operations.
摘要:
A processor array system includes an n-bit scalar processor (2) and an m x m-bit processor array (1), m and n being integers, with m greater than n. The system also includes an array support circuit (3) which is connected between the scalar processor (2) and the processor array (1) and communicates data between them. The system may include an n-bit wide data path linking n-bit scalar processor registers in the scalar processor to the array support circuit (3) together with an m-bit wide data path linking the array support circuit (3) to the processor array (1). The array support circuit (3) includes a register interface arranged to interface the n-bit scalar processor registers to the processor array (1). The array support circuit (3) also includes an m-bit wide edge registers (ME) which is connected to the processor array (1) via the m-bit wide data path. The array may employ an SIMD architecture with each of a number of single bit processing elements having associated with it local store.
摘要:
A vibration damper assembly for damping non-synchronous vibration between adjacent, spaced apart components comprises a vibration damper located in both of a pair of generally confronting passages in each of the components. The assembly comprises at least two spaced apart articulation surfaces for contact between damper and component, each of the articulation surfaces is arcuate in a first direction and is characterised by having a substantially linear portion in an orthogonal and second direction. Thereby the contact area is greatly enlarged and material loss minimised. The cross-sectional shape of the damper or passage is non-circular and there is a clearance between the damper and passage sufficiently small to prevent rotation of the damper in the passage during use.