-
公开(公告)号：USD596450S1
公开(公告)日：2009-07-21
申请号：US29331979
申请日：2009-02-06
申请人： David Nolan
设计人： David Nolan
-
公开(公告)号：US20060174108A1
公开(公告)日：2006-08-03
申请号：US11069798
申请日：2005-02-28
申请人： Kevin Loughran , David Nolan , Paul Hough , Philip Pinto
发明人： Kevin Loughran , David Nolan , Paul Hough , Philip Pinto
IPC分类号： H04L9/00
CPC分类号： H04L63/0428 , H04L1/0061 , H04L1/0072 , H04L49/354 , H04L63/164
摘要： Deciphering and verification of the checksum of enciphered and encapsulated UDP datagrams, particularly those which enclose a tunnelling protocol such as L2TP, are achieved by the provision of a checksum verifier in parallel with a decipher block. Checksum logic creates a pseudo UDP header needed for checksum verification using fields that would occur at the start of the packet that encapsulates the UDP datagram. The first part of the packet to be deciphered is the UDP header; checksum logic can latch the checksum field into a local register. As the rest of the packet is deciphered the checksum verifier processes the data at the same time. Eventually the checksum logic will acquire a complete checksum which can be compared with the checksum that had been previously latched, so as to verify the checksum.
摘要翻译： 对加密和封装的UDP数据报的校验和进行解密和验证，特别是包含诸如L2TP的隧道协议的UDP数据报，通过与解密块并行提供校验和来实现。 校验和逻辑使用在封装UDP数据报的数据包开始时发生的字段来创建校验和验证所需的伪UDP头。 要解密的数据包的第一部分是UDP报头; 校验和逻辑可以将校验和字段锁定到本地寄存器中。 当数据包的其余部分被解密时，校验和验证器同时处理数据。 最终，校验和逻辑将获得一个完整的校验和，可以将之与之前锁存的校验和进行比较，以验证校验和。
-
公开(公告)号：US06707980B2
公开(公告)日：2004-03-16
申请号：US10061601
申请日：2002-01-31
IPC分类号： G02B600
CPC分类号： G02B6/266 , G02B6/3869
摘要： A variable attenuation device for optical signal transmission has first and second ferrules or plugs having abutting end faces, one of the ferrules being rotatable with respect to the other while axial alignment therebetween is maintained. Each ferrule or plug has an axial bore aligned with the other and contains the end of an optical fiber, with a fiber having a smaller diameter than the diameter of the bore in which it is contained so that the fibers may have decreased engagement with each other when there is relative rotation of the ferrules although the ferrule bores remain aligned.
摘要翻译： 用于光信号传输的可变衰减装置具有第一和第二套圈或插塞，其具有邻接的端面，一个套圈可相对于另一个旋转，同时保持其间的轴向对准。 每个套管或插头具有与另一个对准的轴向孔，并且包含光纤的端部，其中纤维的直径小于其所包含的孔的直径，使得纤维可以彼此减小的接合 当套圈相对旋转时，套管孔保持对准。
-
公开(公告)号：USD596445S1
公开(公告)日：2009-07-21
申请号：US29330514
申请日：2009-01-08
申请人： David Nolan
设计人： David Nolan
-
5.发明授权公开(公告)号：US06807175B1
公开(公告)日：2004-10-19
申请号：US09645569
申请日：2000-08-25
申请人： Kevin Jennings , Jerome Nolan , David Nolan , Michael J Gleeson
发明人： Kevin Jennings , Jerome Nolan , David Nolan , Michael J Gleeson
IPC分类号： H04L1256
CPC分类号： H04L45/00 , H04L12/18 , H04L12/4625 , H04L12/467 , H04L45/16 , H04Q11/04 , H04Q2213/13196 , H04Q2213/13242 , H04Q2213/13296 , H04Q2213/13336 , H04Q2213/13389
摘要： A network router has a distributed processing scheme for multicast packets. The router has a look-up and forwarding engine operative in response to the reception of an internet protocol multicast packet to direct the packet to a multiplicity of transmit ports which may or may not be connected to the source network segment from which the multicast packet was received by the router. Each transmit port is associated with a predetermined default network segment and the engine directs the packet to the ports (e.g. across the router's backplane) with an identification of the source network segment and control flags which enable processing means associated with the ports to determine by comparison of the respective network segment and the source network segment whether the packet is bridged from the respective port or routed, with relevant modification of the packet, from that port. The control flags comprises a first flag which can be set to allow the relevant modification and a second flag which can be set to allow the comparison between the source segment and the predetermined default segment.
摘要翻译： 网络路由器具有用于组播数据包的分布式处理方案。 路由器具有响应于互联网协议组播分组的接收而工作的查找和转发引擎，以将分组引导到可以或可以不连接到多播分组的源网络段的多个发送端口 由路由器接收。 每个发送端口与预定的默认网段相关联，并且引擎将分组引导到端口（例如跨越路由器的背板），其中源网络段和控制标志的标识使得与端口相关联的处理装置能够通过比较来确定 各个网段和源网段是否从该端口与相应端口桥接或通过相关的数据包修改路由。 控制标志包括可被设置为允许相关修改的第一标志和可被设置为允许源段与预定默认段之间的比较的第二标志。
-
公开(公告)号：US06675366B1
公开(公告)日：2004-01-06
申请号：US10375831
申请日：2003-02-25
申请人： Stephen David Nolan
发明人： Stephen David Nolan
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F17/5022 , G06F2217/74
摘要： A system and method for designing schematic diagrams of electronic circuits is provided. A library of electronic components represented in graphical form are selectable by a user for inclusion into a schematic diagram. The components are connected together to define a circuit that performs a function. In order to simulate and test a particular portion of the circuit rather than the entire circuit, the present invention provides a disabling routine that disables portions of the circuit not to be included in the simulation. The present invention allows a circuit designer/tester to focus on desired areas of a circuit while ignoring others.
摘要翻译： 提供了一种用于设计电子电路原理图的系统和方法。 以图形形式表示的电子部件库可由用户选择以包含在示意图中。 组件连接在一起以定义执行功能的电路。 为了模拟和测试电路的特定部分，而不是整个电路，本发明提供了禁用不被包括在仿真中的电路的部分的禁用例程。 本发明允许电路设计者/测试者在忽略其他电路的同时专注于电路的所需区域。
-
公开(公告)号：US06546536B1
公开(公告)日：2003-04-08
申请号：US09916072
申请日：2001-07-26
申请人： Stephen David Nolan
发明人： Stephen David Nolan
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F17/5022 , G06F2217/74
摘要： A system and method for designing schematic diagrams of electronic circuits is provided. A library of electronic components represented in graphical form are selectable by a user for inclusion into a schematic diagram. The components are connected together to define a circuit that performs a function. In order to simulate and test a particular portion of the circuit rather than the entire circuit, the present invention provides a disabling routine that disables portions of the circuit not to be included in the simulation. The present invention allows a circuit designer/tester to focus on desired areas of a circuit while ignoring others.
摘要翻译： 提供了一种用于设计电子电路原理图的系统和方法。 以图形形式表示的电子部件库可由用户选择以包含在示意图中。 组件连接在一起以定义执行功能的电路。 为了模拟和测试电路的特定部分，而不是整个电路，本发明提供了禁用不被包括在仿真中的电路的部分的禁用例程。 本发明允许电路设计者/测试者在忽略其他电路的同时专注于电路的所需区域。
-
公开(公告)号：US07843910B2
公开(公告)日：2010-11-30
申请号：US11069798
申请日：2005-02-28
申请人： Kevin Loughran , David Nolan , Paul Hough , Philip Pinto
发明人： Kevin Loughran , David Nolan , Paul Hough , Philip Pinto
CPC分类号： H04L63/0428 , H04L1/0061 , H04L1/0072 , H04L49/354 , H04L63/164
摘要： Deciphering and verification of the checksum of enciphered and encapsulated UDP datagrams, particularly those which enclose a tunneling protocol such as L2TP, are achieved by the provision of a checksum verifier in parallel with a decipher block. Checksum logic creates a pseudo UDP header needed for checksum verification using fields that would occur at the start of the packet that encapsulates the UDP datagram. The first part of the packet to be deciphered is the UDP header; checksum logic can latch the checksum field into a local register. As the rest of the packet is deciphered the checksum verifier processes the data at the same time. Eventually the checksum logic will acquire a complete checksum which can be compared with the checksum that had been previously latched, so as to verify the checksum.
摘要翻译： 对加密和封装的UDP数据报的校验和进行解密和验证，特别是包含诸如L2TP的隧道协议的UDP数据报，通过与解密块并行提供校验和来实现。 校验和逻辑使用在封装UDP数据报的数据包开始时发生的字段来创建校验和验证所需的伪UDP头。 要解密的数据包的第一部分是UDP报头; 校验和逻辑可以将校验和字段锁定到本地寄存器中。 当数据包的其余部分被解密时，校验和验证器同时处理数据。 最终，校验和逻辑将获得一个完整的校验和，可以将之与之前锁存的校验和进行比较，以验证校验和。
-
公开(公告)号：US06025727A
公开(公告)日：2000-02-15
申请号：US196193
申请日：1998-11-20
申请人： Stuart Louis Inkpen , Dana Charles Linfield , Christopher David Nolan , John Charles Ebenezer Hall , Christopher Hext Marshall , Heather Lynn Spearns
发明人： Stuart Louis Inkpen , Dana Charles Linfield , Christopher David Nolan , John Charles Ebenezer Hall , Christopher Hext Marshall , Heather Lynn Spearns
CPC分类号： G01N33/365
摘要： A device and method for measuring changes in denier, percent finish-on-yarn, interlacing of polymer fiber, and other fiber properties, in real time as the fiber is being manufactured. The device uses an electrode driven at a discrete voltage to induce a current which changes in amplitude and/or phase in response to changes in denier, finish-on-yarn and/or interlacing of a fiber. A sensing system samples the current and detects changes in the amplitude and/or phase. A computer, running an application program, quantifies the change and determines the applicable property.
摘要翻译： 一种用于在制造纤维时实时测量旦尼尔变化，纱线完成率，聚合物纤维交织和其它纤维特性的装置和方法。 器件使用以离散电压驱动的电极，以响应纤维的旦数，纱线整理和/或交织的变化而引起振幅和/或相位的变化的电流。 感测系统对电流进行采样并检测振幅和/或相位的变化。 运行应用程序的计算机量化变化并确定适用的属性。
-
公开(公告)号：USD600508S1
公开(公告)日：2009-09-22
申请号：US29330527
申请日：2009-01-08
申请人： David Nolan
设计人： David Nolan
-
-
-
-
-
-
-
-
-
搜索结果
20 条记录 (耗时 0.013 秒)
