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公开(公告)号：US08358987B2
公开(公告)日：2013-01-22
申请号：US11529071
申请日：2006-09-28
IPC分类号： H04B1/18
CPC分类号： H04B1/707 , H04L1/0045 , H04L1/0071
摘要： A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data, an intermediate frame buffer that receives the de-mapped physical channel data, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data, a CRC checker and an output buffer.
摘要翻译： 无线系统中的比特率处理器包括用于处理物理信道数据并生成编码的传输信道数据的前端处理器，用于保存经编码的传输信道数据的传输信道缓冲器和用于处理编码的传输信道数据的后端处理器 并且生成解码的传输信道位。 前端处理可以包括接收物理信道数据的帧缓冲器，去映射物理信道数据的第一级，接收去映射物理信道数据的中间帧缓冲器，以及处理该去映射物理信道数据的第二级 并且提供编码的传输信道数据。 后端处理器可以包括第三级，包括缩放所编码的传输信道数据的缩放电路，解码器以解码缩放的传输信道数据，CRC校验器和输出缓冲器。
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2.再颁专利Method of sending feedback information in a fast automatic repeat request forming part of an overall wireless communication system 有权在构成整个无线通信系统的一部分的快速自动重复请求中发送反馈信息的方法公开(公告)号：USRE42744E1
公开(公告)日：2011-09-27
申请号：US11267890
申请日：2005-11-04
申请人： Esa Malkamaki , Deepak Mathew , Kari Pehkonen , Jussi Kahtava
发明人： Esa Malkamaki , Deepak Mathew , Kari Pehkonen , Jussi Kahtava
IPC分类号： H04B1/44
CPC分类号： H04L1/0068 , H04L1/0025 , H04L1/0028 , H04L1/0071 , H04L1/0073 , H04L1/1671 , H04L1/1812 , H04L1/1845
摘要： A method of sending feedback information in a fast physical layer hybrid automatic repeat request (HARQ) for frequency division duplex communications that form an overall wireless communication system is described in which the received packets are acknowledged by transmitting feedback data to the sender, wherein the acknowledgement comprises the reservation of obtaining a plurality of slots in the uplink/downlink dedicated channel radio frame for the feedback data alone. It is also directed to the transmission of feedback data used in specified slots within each radio frame, wherein the first slot used is based upon the time offset between uplink and downlink channels, as well as based upon the time required for de-interleaving, de-ratematching, decoding and error checking. In an alternative embodiment, the method uses dedicated physical control channel (DPCCH) bits in at least some of the slots for transmitting such feedback data to the sender.
摘要翻译： 描述了在形成整体无线通信系统的用于频分双工通信的快速物理层混合自动重传请求（HARQ）中发送反馈信息的方法，其中通过向发送方发送反馈数据来确认所接收的分组，其中确认 包括仅在反馈数据的上行链路/下行链路专用信道无线电帧中获得多个时隙的预留。 它还针对在每个无线电帧内在指定时隙中使用的反馈数据的传输，其中所使用的第一时隙基于上行链路和下行链路信道之间的时间偏移，以及基于去交织所需的时间，de - 匹配，解码和错误检查。 在替代实施例中，该方法使用至少一些时隙中的专用物理控制信道（DPCCH）比特来将这种反馈数据发送到发送方。
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公开(公告)号：US20090161745A1
公开(公告)日：2009-06-25
申请号：US12189529
申请日：2008-08-11
申请人： Carsten Aagaard Pedersen , John Zijun Shen , Aiguo Yan , Deepak Mathew , Marko Kocic , Timothy Perrin Fisher-Jeffes , Thomas Keller
发明人： Carsten Aagaard Pedersen , John Zijun Shen , Aiguo Yan , Deepak Mathew , Marko Kocic , Timothy Perrin Fisher-Jeffes , Thomas Keller
CPC分类号： H04L27/34 , H04L27/3809
摘要： A system includes a receiver for receiving a modulated signal. The receiver includes a gain estimator for converting complex data representative of constellation points of the modulated signal into scalar data representation. The gain estimator is configured to fold a first portion of the scalar data representation onto a second portion of the scalar data representation. The gain estimator is further configured to estimate a constellation gain value from the folded first portion and the second portion of the scalar data representation.
摘要翻译： 系统包括用于接收调制信号的接收机。 接收机包括用于将表示调制信号的星座点的复数数据转换为标量数据表示的增益估计器。 增益估计器被配置为将标量数据表示的第一部分折叠到标量数据表示的第二部分上。 增益估计器还被配置为从标量数据表示的折叠的第一部分和第二部分估计星座增益值。
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4.发明申请Transport channel buffer organization in downlink receiver bit rate processor 审中-公开下行接收器比特率处理器中的传输信道缓冲器组织公开(公告)号：US20080080444A1
公开(公告)日：2008-04-03
申请号：US11529182
申请日：2006-09-28
IPC分类号： H04B7/216
CPC分类号： H04L49/901 , H04L49/90
摘要： A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data and a CRC checker to provide the decoded transport channel bits, and an output buffer to receive the decoded transport channel bits.
摘要翻译： 无线系统中的比特率处理器包括用于处理物理信道数据并生成编码的传输信道数据的前端处理器，用于保存经编码的传输信道数据的传输信道缓冲器和用于处理编码的传输信道数据的后端处理器 并且生成解码的传输信道位。 前端处理可以包括接收物理信道数据的帧缓冲器，从帧缓冲器去映射物理信道数据的第一级，从第一级接收去映射物理信道数据的中间帧缓冲器， 以及第二级，用于处理去映射的物理信道数据并提供经编码的传输信道数据。 后端处理器可以包括第三级，包括缩放经编码的传输信道数据的缩放电路，解码器以解码缩放的传输信道数据和CRC校验器以提供解码的传输信道位，以及输出缓冲器，用于接收 解码的传输信道位。
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公开(公告)号：US07277474B2
公开(公告)日：2007-10-02
申请号：US10625479
申请日：2003-07-23
申请人： Abhay Sharma , Zoran Zvonar , Deepak Mathew , Aiguo Yan
发明人： Abhay Sharma , Zoran Zvonar , Deepak Mathew , Aiguo Yan
IPC分类号： H04B1/707
CPC分类号： H04B1/7117 , H04B1/7113 , H04B2201/7071
摘要： A technique for allocating fingers in a path searcher of a multipath receiver involves determining a required number of fingers for each multipath region, determining a number of allocated fingers for each multipath region according to an area-based weighting scheme such that each multipath region that is allocated fewer than its required number of fingers is deemed to have a non-zero residual area, allocating any surplus fingers to multipath regions having non-zero residual areas until either no surplus fingers remain or each multipath region is allocated its required number of fingers, and placing any fingers allocated to each multipath region within the multipath region. Placing the fingers in un-resolvable path scenario involves detecting path location at the edges of multipath region; placing fingers at the edges and placing remaining fingers uniformly between the first and the last path such that the there is a minimum placement separation between the fingers.
摘要翻译： 一种用于在多路径接收机的路径搜索器中分配手指的技术包括确定每个多径区域的所需数量的手指，根据基于区域的加权方案确定每个多径区域的分配的手指的数量，使得每个多径区域是 分配少于其所需数量的手指被认为具有非零残余区域，将任何剩余手指分配给具有非零残余区域的多径区域，直到没有剩余的手指保留，或者每个多径区域被分配其所需数量的手指， 并且分配给多径区域内的每个多径区域的任何手指。 将手指放在不可解决的路径场景中涉及检测多径区域边缘的路径位置; 将手指放置在边缘并将剩余的手指均匀地放置在第一和最后路径之间，使得手指之间存在最小的放置间隔。
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6.发明授权Method of sending feedback information in a fast automatic repeat request forming part of an overall wireless communication system 有权在构成整个无线通信系统的一部分的快速自动重复请求中发送反馈信息的方法公开(公告)号：US06735180B1
公开(公告)日：2004-05-11
申请号：US09608643
申请日：2000-06-30
申请人： Esa Malkamäki , Deepak Mathew , Kari Pehkonen , Jussi Kähtävä
发明人： Esa Malkamäki , Deepak Mathew , Kari Pehkonen , Jussi Kähtävä
IPC分类号： H04B144
CPC分类号： H04L1/0068 , H04L1/0025 , H04L1/0028 , H04L1/0071 , H04L1/0073 , H04L1/1671 , H04L1/1812 , H04L1/1845
摘要： A method of sending feedback information in a fast physical layer hybrid automatic repeat request (HARQ) for frequency division duplex communications that form an overall wireless communication system is described in which the received packets are acknowledged by transmitting feedback data to the sender, wherein the acknowledgement comprises the reservation of obtaining a plurality of slots in the uplink/downlink dedicated channel radio frame for the feedback data alone. It is also directed to the transmission of feedback data used in specified slots within each radio frame, wherein the first slot used is based upon the time offset between uplink and downlink channels, as well as based upon the time required for de-interleaving, de-ratematching, decoding and error checking. In an alternative embodiment, the method uses dedicated physical control channel (DPCCH) bits in at least some of the slots for transmitting such feedback data to the sender.
摘要翻译： 描述了在形成整体无线通信系统的用于频分双工通信的快速物理层混合自动重传请求（HARQ）中发送反馈信息的方法，其中通过向发送方发送反馈数据来确认所接收的分组，其中确认 包括仅在反馈数据的上行链路/下行链路专用信道无线电帧中获得多个时隙的预留。 它还针对在每个无线电帧内在指定时隙中使用的反馈数据的传输，其中所使用的第一时隙基于上行链路和下行链路信道之间的时间偏移，以及基于去交织所需的时间，de - 匹配，解码和错误检查。 在替代实施例中，该方法使用至少一些时隙中的专用物理控制信道（DPCCH）比特来将这种反馈数据发送到发送方。
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公开(公告)号：US20140059323A1
公开(公告)日：2014-02-27
申请号：US13592617
申请日：2012-08-23
IPC分类号： G06F15/76
CPC分类号： G06F15/8084 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30109
摘要： Systems and methods of data extraction in a vector processor are disclosed. In a particular embodiment a method of data extraction in a vector processor includes copying at least one data element to a source register of a permutation network. The method includes reordering multiple data elements of the source register, populating a destination register of the permutation network with the reordered data elements, and copying the reordered data elements from the destination register to a memory.
摘要翻译： 公开了一种向量处理器中数据提取的系统和方法。 在特定实施例中，向量处理器中的数据提取方法包括将至少一个数据元素复制到置换网络的源寄存器。 该方法包括重新排序源寄存器的多个数据元素，用重新排序的数据元素填充置换网络的目的地寄存器，以及将重新排序的数据元素从目的地寄存器复制到存储器。
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8.发明授权Interface between chip rate processing and bit rate processing in wireless downlink receiver 有权无线下行接收机芯片速率处理与比特率处理之间的接口公开(公告)号：US08358988B2
公开(公告)日：2013-01-22
申请号：US11529146
申请日：2006-09-28
申请人： Lidwine Martinot , Deepak Mathew , Krishnan Vishwanathan , Eric Aardoom , Aiguo Yan , Timothy Fisher-Jeffes
发明人： Lidwine Martinot , Deepak Mathew , Krishnan Vishwanathan , Eric Aardoom , Aiguo Yan , Timothy Fisher-Jeffes
IPC分类号： H04B1/18
CPC分类号： H04B1/7105 , H04B2201/70707
摘要： A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data, an intermediate frame buffer that receives the de-mapped physical channel data, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data, a CRC checker and an output buffer.
摘要翻译： 无线系统中的比特率处理器包括用于处理物理信道数据并生成编码的传输信道数据的前端处理器，用于保存经编码的传输信道数据的传输信道缓冲器和用于处理编码的传输信道数据的后端处理器 并且生成解码的传输信道位。 前端处理可以包括接收物理信道数据的帧缓冲器，去映射物理信道数据的第一级，接收去映射物理信道数据的中间帧缓冲器，以及处理该去映射物理信道数据的第二级 并且提供编码的传输信道数据。 后端处理器可以包括第三级，包括缩放所编码的传输信道数据的缩放电路，解码器以解码缩放的传输信道数据，CRC校验器和输出缓冲器。
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公开(公告)号：US20090161648A1
公开(公告)日：2009-06-25
申请号：US12194516
申请日：2008-08-19
申请人： Deepak MATHEW , Russ MESTECHKIN , Prahallada PONNATHOTA , Thomas F. HOWE , Timothy Perrin FISHER-JEFFES
发明人： Deepak MATHEW , Russ MESTECHKIN , Prahallada PONNATHOTA , Thomas F. HOWE , Timothy Perrin FISHER-JEFFES
IPC分类号： H04W74/02
CPC分类号： H04B1/707 , G06F5/16 , G11C7/1075 , H04B2201/70707
摘要： A wireless device has a BRP-CRP interface that includes a dual-port frame memory having a first access port and a second access port in which data can be written to the dual-port frame memory through the first access port at the same time that data is read from the dual-port frame memory through the second access port. A bit rate processor performs bit rate processing on input data and writes data resulting from the bit rate processing to the dual-port frame memory through the first access port. A chip rate processor reads data from the dual-port frame memory through the second access port and performs chip rate processing on the data read from the dual-port frame memory. A data processor executes a software application that writes data to the dual-port frame memory through the first access port and reads data from the dual-port frame memory through the second access port.
摘要翻译： 无线设备具有BRP-CRP接口，其包括具有第一接入端口和第二接入端口的双端口帧存储器，其中可以通过第一接入端口将数据写入双端口帧存储器，同时该 通过第二个访问端口从双端口帧存储器中读取数据。 比特率处理器对输入数据执行比特率处理，并将通过比特率处理产生的数据通过第一接入端口写入双端口帧存储器。 芯片速率处理器通过第二访问端口从双端口帧存储器读取数据，并对从双端口帧存储器读取的数据执行码片速率处理。 数据处理器执行通过第一访问端口将数据写入双端口帧存储器的软件应用程序，并通过第二访问端口从双端口帧存储器读取数据。
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公开(公告)号：US20080081575A1
公开(公告)日：2008-04-03
申请号：US11529071
申请日：2006-09-28
IPC分类号： H04B1/18
CPC分类号： H04B1/707 , H04L1/0045 , H04L1/0071
摘要： A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data and a CRC checker to provide the decoded transport channel bits, and an output buffer to receive the decoded transport channel bits.
摘要翻译： 无线系统中的比特率处理器包括用于处理物理信道数据并生成编码的传输信道数据的前端处理器，用于保存经编码的传输信道数据的传输信道缓冲器和用于处理编码的传输信道数据的后端处理器 并且生成解码的传输信道位。 前端处理可以包括接收物理信道数据的帧缓冲器，从帧缓冲器去映射物理信道数据的第一级，从第一级接收去映射物理信道数据的中间帧缓冲器， 以及第二级，用于处理去映射的物理信道数据并提供经编码的传输信道数据。 后端处理器可以包括第三级，包括缩放经编码的传输信道数据的缩放电路，解码器以解码缩放的传输信道数据和CRC校验器以提供解码的传输信道位，以及输出缓冲器，用于接收 解码的传输信道位。
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