公开(公告)号：US20080170571A1

公开(公告)日：2008-07-17

申请号：US11622699

申请日：2007-01-12

申请人： Dhiraj Kumar ,  Kanwar Jit Singh

发明人： Dhiraj Kumar ,  Kanwar Jit Singh

IPC分类号： H04L12/56

CPC分类号： H04L49/9047 ,  H04L49/3072 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9042

摘要： A method and system for synchronous page addressing in a data packet switch is provided. Within the packet switch, separate devices are responsible for storing a portion of a received data packet, and thus a view of used memory addresses seen by one device matches that seen by the others. Each device uses the same order of memory addresses to write data so that bytes of data are stored as a linked-list of pages. Maintaining the same sequence of page requests and sequence of free-page addresses to which to write these pages ensures consistent addressing of the portions of the data packet.

摘要翻译： 提供了一种用于在数据分组交换机中同步寻址的方法和系统。 在分组交换机内，单独的设备负责存储接收到的数据分组的一部分，因此一个设备看到的已使用的存储器地址的视图与其他设备所看到的匹配。 每个设备使用相同的存储器地址顺序来写入数据，使得数据字节被存储为页面的链接列表。 维护相同的页面请求序列和自由页面地址序列来写入这些页面，确保数据包部分的一致寻址。

公开(公告)号：US20070011396A1

公开(公告)日：2007-01-11

申请号：US11172114

申请日：2005-06-30

申请人： Kanwar Singh ,  Dhiraj Kumar

发明人： Kanwar Singh ,  Dhiraj Kumar

IPC分类号： G06F13/28

CPC分类号： G06F13/4059

摘要： A system and method for buffering data packets in a data network device having a DRAM buffer are presented. When writing packets, the buffering system separates available memory channels into two groups corresponding to ingress and egress data. Based on the source of the data packets, data pages from the data packets are assigned to channels from either the ingress or egress group. Non-conflicting sets of addresses, called cachelines, are requested on each memory channel, and the data pages are evenly distributed over the assigned channels before being mapped to a cacheline. The number of read transactions currently being monitored by the system is controlled in order to reduce random packet read conflicts. Additionally, write and read transactions are grouped by an arbitration unit prior to being sent to the DRAM controller.

摘要翻译： 提出了一种用于在具有DRAM缓冲器的数据网络设备中缓冲数据分组的系统和方法。 当写入数据包时，缓冲系统将可用存储器通道分为两个对应于入口和出口数据的组。 基于数据包的来源，来自数据包的数据页被分配给来自入口或出口组的信道。 在每个存储器通道上请求非冲突的地址集合，称为高速缓存线，并且数据页在映射到高速缓存线之前均匀分布在所分配的通道上。 控制系统当前正在监视的读取事务的数量，以便减少随机数据包读取冲突。 此外，写入和读取事务在发送到DRAM控制器之前由仲裁单元分组。

公开(公告)号：US5974255A

公开(公告)日：1999-10-26

申请号：US137704

申请日：1993-10-18

申请人： Dhiraj Kumar Gossain ,  Dana Mark Rigg

发明人： Dhiraj Kumar Gossain ,  Dana Mark Rigg

IPC分类号： G06F9/44 ,  G06F9/455

CPC分类号： G06F9/4433

摘要： An object oriented test provides a hierarchy of classes under test, each of the classes under test having a predefined inheritance structure. The test provides a test class for each corresponding class under test. Each class under test has a test member function, a set state member function, a verify state member function, and a test vector which includes an initial complete state, an expected complete state, a set of function inputs for a member function being tested, and a set of expected results. The test sets an initial complete state of the test class by implicitly calling the set state member functions through the inheritance structure of the test classes. Next a member function of a desired class under test is executed. The final complete state of the class under test as well as the outputs and returned values of all member functions which were executed are compared with the set of expected results.

摘要翻译： 面向对象的测试提供了被测试类的层次结构，每个受测类都具有预定义的继承结构。 该测试为每个相应的被测课程提供一个测试类。 被测试的每个类具有测试成员函数，设置状态成员函数，验证状态成员函数和包括初始完成状态，预期完成状态，正被测试的成员函数的一组功能输入的测试向量， 和一组预期成果。 测试通过隐含地通过测试类的继承结构调用集合状态成员函数来设置测试类的初始完成状态。 接下来，执行所需的被测试类的成员函数。 将所执行的所有成员函数的最终完整状态以及所有成员函数的输出和返回值与预期结果的集合进行比较。

公开(公告)号：US20090285011A1

公开(公告)日：2009-11-19

申请号：US12120980

申请日：2008-05-15

申请人： Dhiraj Kumar Pradhan ,  Jawar Singh ,  Jimson Mathew

发明人： Dhiraj Kumar Pradhan ,  Jawar Singh ,  Jimson Mathew

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C11/412

摘要： A static random access memory (“SRAM”) comprising: a pair of inverters each having an input and an output; a cross-coupling path coupling the input of a first inverter to the output of a second inverter; and a transmission gate, wherein the transmission gate comprises a p-channel transistor coupling the input of the second inverter to the output of the first inverter; and an n-channel transistor coupling the input of the second inverter to the output of the first inverter in parallel with the p-channel transistor. In another embodiment, the SRAM comprises a first inverter having a supply voltage node connected to a supply voltage, and a ground node connected to ground; a second inverter cross-coupled with the first inverter and having a supply voltage node connected to a supply voltage, and a ground node; and a switch selectively connecting and disconnecting the ground node of the second inverter to ground.

摘要翻译： 一种静态随机存取存储器（“SRAM”），包括：一对具有输入和输出的反相器; 将第一反相器的输入耦合到第二反相器的输出的交叉耦合路径; 以及传输门，其中所述传输门包括将所述第二反相器的输入耦合到所述第一反相器的输出的p沟道晶体管; 以及与p沟道晶体管并联的将第二反相器的输入耦合到第一反相器的输出的n沟道晶体管。 在另一实施例中，SRAM包括具有连接到电源电压的电源电压节点的第一反相器和连接到地的接地节点; 与第一反相器交叉耦合并具有连接到电源电压的电源电压节点的第二反相器和接地节点; 以及选择性地将第二反相器的接地节点连接到地的开关。

公开(公告)号：US20060268913A1

公开(公告)日：2006-11-30

申请号：US11139070

申请日：2005-05-27

申请人： Kanwar Singh ,  Dhiraj Kumar

发明人： Kanwar Singh ,  Dhiraj Kumar

IPC分类号： H04L12/28 ,  H04J3/24 ,  H04L12/56

CPC分类号： H04L49/9073 ,  H04L49/90 ,  H04L49/9042 ,  H04L69/12

摘要： A system for streaming incoming data packets into a buffer memory is presented. The system may receive incoming data packets over a variety of interfaces and separate the data packet into a header page and one or more data page. The system may interface with a header processor and send header pages to the header processor to be modified. Data pages from the incoming data packets are streamed to a central staging memory, allowing the use of a simple first-in-first-out (FIFO) buffer. The system may receive modified headers from the header processor and provide multiple copies of data packets for multicast or sampling purposes. Data packet copies may then be written to an external memory buffer over one or more external memory channels. The system may also provide an error recovery process to account for corrupt data packets streamed to the external memory buffer.

摘要翻译： 提出了一种将输入数据包流入缓冲存储器的系统。 系统可以通过各种接口接收输入数据分组，并将数据分组分离成头部页面和一个或多个数据页面。 该系统可以与头部处理器接口，并将头部页面发送到头部处理器以进行修改。 来自传入数据包的数据页被流传输到中央登记存储器，允许使用简单的先进先出（FIFO）缓冲区。 该系统可以从报头处理器接收修改的报头，并提供数据分组的多个副本以进行多播或采样。 然后可以通过一个或多个外部存储器通道将数据分组副本写入外部存储器缓冲器。 该系统还可以提供错误恢复过程来解决流向外部存储器缓冲器的损坏的数据分组。

公开(公告)号：US5678040A

公开(公告)日：1997-10-14

申请号：US759339

申请日：1996-12-02

申请人： Venu Vasudevan ,  Dhiraj Kumar Gossain ,  Dana Mark Rigg ,  Don Michael Gibson ,  Tron Kyle Womack

发明人： Venu Vasudevan ,  Dhiraj Kumar Gossain ,  Dana Mark Rigg ,  Don Michael Gibson ,  Tron Kyle Womack

IPC分类号： G06F17/50 ,  G06Q10/10 ,  G06F15/00

CPC分类号： G06Q10/10 ,  G06F17/50 ,  G06F2217/04 ,  Y10S707/99938 ,  Y10S707/99945 ,  Y10S707/99952 ,  Y10S707/99953

摘要： A hierarchical design transaction method which provides a shared project workspace and an individual user workspace. A desired portion of a hierarchical design is checked out from the shared project workspace and is edited in the individual user workspace. A new version of the desired portion of the hierarchical design is checked into the shared project workspace. Concurrently, another individual user workspace is provided, and another desired portion of the hierarchical design is checked out, edited and checked in. These steps are repeated for each of a plurality of desired portions of the hierarchical design, to continuously guarantee consistency between the shared project workspace and each individual user workspace.

摘要翻译： 提供共享项目工作空间和单个用户工作空间的分层设计事务方法。 从共享项目工作区中检出分层设计的所需部分，并在单个用户工作区中进行编辑。 分层设计的所需部分的新版本被检入共享项目工作空间。 同时，提供了另一个单独的用户工作空间，分层设计的另一个所需部分被检出，编辑和检入。对于分层设计的多个期望部分中的每一个重复这些步骤，以连续地保证共享 项目工作区和每个单独的用户工作区。

公开(公告)号：US07706174B2

公开(公告)日：2010-04-27

申请号：US12120980

申请日：2008-05-15

申请人： Dhiraj Kumar Pradhan ,  Jawar Singh ,  Jimson Mathew

发明人： Dhiraj Kumar Pradhan ,  Jawar Singh ,  Jimson Mathew

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： A static random access memory (“SRAM”) comprising: a pair of inverters each having an input and an output; a cross-coupling path coupling the input of a first inverter to the output of a second inverter; and a transmission gate, wherein the transmission gate comprises a p-channel transistor coupling the input of the second inverter to the output of the first inverter; and an n-channel transistor coupling the input of the second inverter to the output of the first inverter in parallel with the p-channel transistor. In another embodiment, the SRAM comprises a first inverter having a supply voltage node connected to a supply voltage, and a ground node connected to ground; a second inverter cross-coupled with the first inverter and having a supply voltage node connected to a supply voltage, and a ground node; and a switch selectively connecting and disconnecting the ground node of the second inverter to ground.

摘要翻译： 一种静态随机存取存储器（“SRAM”），包括：一对具有输入和输出的反相器; 将第一反相器的输入耦合到第二反相器的输出的交叉耦合路径; 以及传输门，其中所述传输门包括将所述第二反相器的输入耦合到所述第一反相器的输出的p沟道晶体管; 以及与p沟道晶体管并联的将第二反相器的输入耦合到第一反相器的输出的n沟道晶体管。 在另一实施例中，SRAM包括具有连接到电源电压的电源电压节点的第一反相器和连接到地的接地节点; 与第一反相器交叉耦合并具有连接到电源电压的电源电压节点的第二反相器和接地节点; 以及选择性地将第二反相器的接地节点连接到地的开关。