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    System for reducing main memory access time by bypassing address expansion device when high-order address portions are unaltered
    1.
    发明授权
    System for reducing main memory access time by bypassing address expansion device when high-order address portions are unaltered 失效
    用于通过在高位地址部分不变时绕过地址扩展设备来减少主存储器访问时间的系统

    公开(公告)号：US4969086A

    公开(公告)日：1990-11-06

    申请号：US376148

    申请日：1989-07-05

    申请人： Klaus Pfeiffer ,  Wolfgang Kosler ,  Gerd Trimpop ,  Erich Paulmichl

    发明人： Klaus Pfeiffer ,  Wolfgang Kosler ,  Gerd Trimpop ,  Erich Paulmichl

    IPC分类号： G06F12/02 ,  G06F12/06

    CPC分类号： G06F12/0215 ,  G06F12/0623

    摘要： Proceeding from a known method and apparatus for expanding the address for accessing a main memory by a central controller of a switching system, a determination is made in a comparator as to whether the address information of the high-order address lines or address registers of the expansion device with respect to a preceding main memory access changes in comparison to the current main memory access. When coincidence is present, the high-order portion of the main memory address in the preceding main memory access stored in an address register is immediately used for the formation of the overall main memory address.

    摘要翻译： 从用于扩展由交换系统的中央控制器访问主存储器的地址的已知方法和装置，在比较器中确定高位地址线的地址信息或地址寄存器是否为 相对于前一主存储器访问的扩展装置与当前主存储器访问相比变化。 当存在一致时，存储在地址寄存器中的前一主存储器访问中的主存储器地址的高阶部分立即用于形成总体主存储器地址。