公开(公告)号：US4969086A

公开(公告)日：1990-11-06

申请号：US376148

申请日：1989-07-05

申请人： Klaus Pfeiffer ,  Wolfgang Kosler ,  Gerd Trimpop ,  Erich Paulmichl

发明人： Klaus Pfeiffer ,  Wolfgang Kosler ,  Gerd Trimpop ,  Erich Paulmichl

IPC分类号： G06F12/02 ,  G06F12/06

CPC分类号： G06F12/0215 ,  G06F12/0623

摘要： Proceeding from a known method and apparatus for expanding the address for accessing a main memory by a central controller of a switching system, a determination is made in a comparator as to whether the address information of the high-order address lines or address registers of the expansion device with respect to a preceding main memory access changes in comparison to the current main memory access. When coincidence is present, the high-order portion of the main memory address in the preceding main memory access stored in an address register is immediately used for the formation of the overall main memory address.

摘要翻译： 从用于扩展由交换系统的中央控制器访问主存储器的地址的已知方法和装置，在比较器中确定高位地址线的地址信息或地址寄存器是否为 相对于前一主存储器访问的扩展装置与当前主存储器访问相比变化。 当存在一致时，存储在地址寄存器中的前一主存储器访问中的主存储器地址的高阶部分立即用于形成总体主存储器地址。

公开(公告)号：US5109330A

公开(公告)日：1992-04-28

申请号：US29685

申请日：1987-03-24

申请人： Klaus Pfeiffer ,  Wolfgang Kosler ,  Erich Paulmichl

发明人： Klaus Pfeiffer ,  Wolfgang Kosler ,  Erich Paulmichl

IPC分类号： G06F15/16 ,  G06F9/52 ,  G06F12/00 ,  G06F13/18 ,  G06F15/177

CPC分类号： G06F13/18

摘要： In a multi-processor system in which a plurality of microprocessor systems are allocated to a common multi-processor bus in cyclical fashion in a sequence prescribed by priority characterizing numbers assigned to said systems, the priority allocation of bus access is overlaid by a further method that coordiantes the access fo a microprocessor system to a region storing a common data base in a common memory. One of the microprocessor systems functions as the main processor system and is authorized to up-date the data base and all other microprocessor systems function as subsidiary procesors which can read the data base information. Before its access, every microprocessor system accessing the data base communicates a status signal to the other micro-processor systems, this preventing the main processor system from up-dating the data base while one of the subsidiary processor systems is already reading the data base information.

摘要翻译： 在多处理器系统中，多个微处理器系统以按照分配给所述系统的优先级特征号所规定的顺序的循环方式分配给公共多处理器总线，总线访问的优先级分配由另一方法 其将微处理器系统的访问协调到在公共存储器中存储公共数据库的区域。 微处理器系统之一用作主处理器系统，并被授权更新数据库，所有其他微处理器系统作为可读取数据库信息的辅助处理器。 在其访问之前，访问数据库的每个微处理器系统将状态信号传送到其他微处理器系统，这防止主处理器系统与数据库进行更新，而其中一个辅助处理器系统已经在读取数据库信息 。

公开(公告)号：US5754815A

公开(公告)日：1998-05-19

申请号：US508968

申请日：1995-07-28

申请人： Edmund Ernst ,  Wolfgang Kosler

发明人： Edmund Ernst ,  Wolfgang Kosler

IPC分类号： G06F12/06 ,  G06F12/0879 ,  G06F12/02

CPC分类号： G06F12/0607 ,  G06F12/0879

摘要： The method controls the sequence (Q) of accesses (Z) of a processor (MP) to an allocated memory (SP) that is formed by at least two individually addressable, static sub-memories or, respectively, memory banks (SRAM 0, 1). Using a drive logic (ASL) inserted between the processor (MP) and, for example, two sub-memories (SRAM 0, 1), a first memory address (sa1) is switched in conformity with an access cycle to the addressed sub-memory (SRAM 0, 1) in a first access (Z) of a sequence (Q), a memory link address (sfa1) for the further sub-memories (SRAM 0, 1) is formed, is switched thereto and a reading or writing of a data (d) is initiated based on the criterion of the status information (sti). Subsequently, the sub-memories (SRAM 0, 1) are cyclically successively driven, a respective data (d) is read or stored using an intermediate memory (ZSP) and a memory link address (sfa2, 3) is respectively formed such that the two sub-memories (SRAM 0, 1) are successively and cyclically driven. As a result of the method, an especially advantageous memory design for communication systems (KS), particularly for telecommunication private branch exchanges, is realized with static sub-memories (SRAM 0, 1), whereby the memory accesses (Z) of a sequence (Q) of accesses (Z) occur at maximum processor access speed.

摘要翻译： 该方法将处理器（MP）的访问（Z）的序列（Q）控制到由至少两个可单独寻址的静态子存储器或分别由存储器组（SRAM 0， 1）。 使用插入在处理器（MP）和例如两个子存储器（SRAM0,1）之间的驱动逻辑（ASL），第一存储器地址（sa1）被切换为与寻址子存储器 形成序列（Q）的第一访问（Z）中的存储器（SRAM0,1），形成其它子存储器（SRAM0,1）的存储器链接地址（sfa1），并将其读取或 基于状态信息（sti）的标准开始写入数据（d）。 随后，子存储器（SRAM0,1）被循环地依次驱动，使用中间存储器（ZSP）读取或存储相应的数据（d），并且分别形成存储器链接地址（sfa2,3），使得 两个子存储器（SRAM 0，1）被连续循环地驱动。 作为该方法的结果，用静态子存储器（SRAM 0,1）实现了用于通信系统（KS），特别是用于电信专用交换机的特别有利的存储器设计，由此存储器访问（Z）序列 （Q）访问（Z）以最大的处理器访问速度发生。