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公开(公告)号：US10309934B2
公开(公告)日：2019-06-04
申请号：US15472449
申请日：2017-03-29
摘要： Disclosed is an ultrasonic non-destructive testing and inspection system and method for determining acoustic velocities in a test object. Beams of acoustic energy from firing an element of an emitting probe propagate in a first wedge, and a beam incident at the critical angle generates a surface wave in the test object. The surface wave propagates to a second wedge and signals are received at receiving elements of a receiving probe array. When a set of appropriate delays is applied to the receiving elements, the acoustic time-of-flight is the same to all receiving elements. Determination of the appropriate delays and the times-of-flight for P-type surface waves and Rayleigh surface waves enables computation of the P- and S-wave acoustic velocities in the test object. The time-of-flight measurement also enables computation of the separation between the first and second wedges.
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公开(公告)号：US07849430B2
公开(公告)日：2010-12-07
申请号：US12054317
申请日：2008-03-24
申请人： Richard W. Smith , Hang Kwan , Manzurul Khan
发明人： Richard W. Smith , Hang Kwan , Manzurul Khan
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A pruning algorithm for generating a reverse donut model (RDM) for running timing analysis for a block in an IC includes logic to reduce a hierarchical model of the IC to a single level flat model. A block from a plurality of blocks that make up the IC is identified from the single level flat model of the IC. The pruning algorithm is further used to initialize a timer and to define timing constraints associated with each of a plurality of input and output pins associated with the identified block. A RDM for the identified block is generated by identifying and including connectivity information associated with a plurality of input and output pins in an outer boundary of the identified block and at least one layer of interface connection between each of the plurality of input and output pins in the outer layer of the identified block and one or more circuit elements external to the identified block in the IC interfacing with each of the plurality of input and output pins in the identified block. The generated RDM acts as a blackbox for the identified block and is used in place of the identified block for running the timing analysis.
摘要翻译： 用于生成用于对IC中的块运行时序分析的反向环形模型（RDM）的修剪算法包括将IC的分级模型减小到单个级别平面模型的逻辑。 从IC的单级平面型号识别来自构成IC的多个块的块。 修剪算法还用于初始化定时器并且定义与与所识别的块相关联的多个输入和输出引脚中的每一个相关联的定时约束。 通过识别并包括与所识别的块的外边界中的多个输入和输出引脚相关联的连通性信息以及多个输入和输出引脚中的每一个之间的至少一层接口连接来生成用于所识别的块的RDM 所识别的块的外层和IC中所识别的块外部的一个或多个电路元件与所识别的块中的多个输入和输出引脚中的每一个接口连接。 生成的RDM用作识别块的黑盒，并用于代替用于运行时序分析的标识块。
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公开(公告)号：US20090241081A1
公开(公告)日：2009-09-24
申请号：US12054317
申请日：2008-03-24
申请人： Richard W. Smith , Hang Kwan , Manzurul Khan
发明人： Richard W. Smith , Hang Kwan , Manzurul Khan
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A pruning algorithm for generating a reverse donut model (RDM) for running timing analysis for a block in an IC includes logic to reduce a hierarchical model of the IC to a single level flat model. A block from a plurality of blocks that make up the IC is identified from the single level flat model of the IC. The pruning algorithm is further used to initialize a timer and to define timing constraints associated with each of a plurality of input and output pins associated with the identified block. A RDM for the identified block is generated by identifying and including connectivity information associated with a plurality of input and output pins in an outer boundary of the identified block and at least one layer of interface connection between each of the plurality of input and output pins in the outer layer of the identified block and one or more circuit elements external to the identified block in the IC interfacing with each of the plurality of input and output pins in the identified block. The generated RDM acts as a blackbox for the identified block and is used in place of the identified block for running the timing analysis.
摘要翻译： 用于生成用于对IC中的块运行时序分析的反向环形模型（RDM）的修剪算法包括将IC的分级模型减小到单个级别平面模型的逻辑。 从IC的单级平面型号识别来自构成IC的多个块的块。 修剪算法还用于初始化定时器并且定义与与所识别的块相关联的多个输入和输出引脚中的每一个相关联的定时约束。 通过识别并包括与所识别的块的外边界中的多个输入和输出引脚相关联的连通性信息以及多个输入和输出引脚中的每一个之间的至少一层接口连接来生成用于所识别的块的RDM 所识别的块的外层和IC中所识别的块外部的一个或多个电路元件与所识别的块中的多个输入和输出引脚中的每一个接口连接。 生成的RDM用作识别块的黑盒，并用于代替用于运行时序分析的标识块。
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公开(公告)号：US20180284069A1
公开(公告)日：2018-10-04
申请号：US15472449
申请日：2017-03-29
CPC分类号： G01N29/07 , G01N29/0645 , G01N29/262 , G01N29/30 , G01N2291/011 , G01N2291/0423 , G01N2291/102
摘要： Disclosed is an ultrasonic non-destructive testing and inspection system and method for determining acoustic velocities in a test object. Beams of acoustic energy from firing an element of an emitting probe propagate in a first wedge, and a beam incident at the critical angle generates a surface wave in the test object. The surface wave propagates to a second wedge and signals are received at receiving elements of a receiving probe array. When a set of appropriate delays is applied to the receiving elements, the acoustic time-of-flight is the same to all receiving elements. Determination of the appropriate delays and the times-of-flight for P-type surface waves and Rayleigh surface waves enables computation of the P- and S-wave acoustic velocities in the test object. The time-of-flight measurement also enables computation of the separation between the first and second wedges.
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公开(公告)号：US5157282A
公开(公告)日：1992-10-20
申请号：US682571
申请日：1991-04-08
申请人： Randy T. Ong , Suresh M. Menon , Hang Kwan
发明人： Randy T. Ong , Suresh M. Menon , Hang Kwan
IPC分类号： H03K19/003
CPC分类号： H03K19/00361 , H03K19/00346
摘要： The present invention minimizes the noise voltage associated with the switching of output driver transistors of integrated cicruits caused by the rapid change in value of the current, expressed by the term di/dt, from the load into the driver transistors through the package leads. The present invention uses a programmable coarse current control (CCC) circuit and a programmable fine current control (FCC) circuit that control the pull-down output transistors. The FCC creates two time periods, after which it prevents the CCC from controlling an output pull-down transistor. The FCC and the CCC are used to reduce the di/dt dependent voltage noise by controlling the slope and the shape of the output voltage pull-down characteristics.
摘要翻译： 本发明使由电流值（由术语di / dt）从负载通过封装引线的驱动晶体管的快速变化引起的集成电路的输出驱动晶体管的切换相关联的噪声电压最小化。 本发明使用可编程粗电流控制（CCC）电路和控制下拉输出晶体管的可编程微电流控制（FCC）电路。 FCC创建两个时间段，之后它阻止CCC控制输出下拉晶体管。 FCC和CCC用于通过控制斜率和输出电压下拉特性的形状来降低di / dt依赖电压噪声。
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公开(公告)号：US20230003691A1
公开(公告)日：2023-01-05
申请号：US17930464
申请日：2022-09-08
摘要： Systems and methods are disclosed for conducting an ultrasonic-based inspection. The systems and methods perform operations comprising: receiving a plurality of scan plan parameters associated with generating an image of at least one flaw within a specimen based on acoustic echo data obtained using full matrix capture (FMC); applying the plurality of scan plan parameters to an acoustic model, the acoustic model configured to determine a two-way pressure response of a plurality of inspection modes based on specular reflection and diffraction phenomena; generating, by the acoustic model based on the plurality of scan plan parameters, an acoustic region of influence (AROI) comprising an acoustic amplitude sensitivity map for a first inspection mode amongst the plurality of inspection modes; and generating, for display, a first image comprising the AROI associated with the first inspection mode for capturing or inspecting the image of the at least one flaw.
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