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    Depletion mode GaN transistor control circuit and corresponding method
    1.
    发明授权
    Depletion mode GaN transistor control circuit and corresponding method 有权

    公开(公告)号：US11955960B2

    公开(公告)日：2024-04-09

    申请号：US17893684

    申请日：2022-08-23

    申请人： Chip-GaN Power Semiconductor Corporation

    发明人： Ke-Horng Chen ,  Tzu-Hsien Yang ,  Yong-Hwa Wen ,  Kuo-Lin Cheng

    IPC分类号： H03K19/003 ,  H03K17/16

    CPC分类号： H03K17/165 ,  H03K19/00346 ,  H03K19/00361

    摘要： The invention uses the control circuit formed on the silicon wafer to detect the leakage current of transistor formed on the depletion mode GaN wafer and then adjust the gate voltage of the depletion mode GaN transistor according to the detected leakage current. Essentially, the gate voltage is reduced or viewed as made more negative when the detected leakage current is larger a specific value. Thus, the gate voltage can be gradually adjusted to approach a specific threshold voltage that right block the leakage current. In other words, by making the gate voltage more negative when non-zero leakage current is detected and even by making the gate voltage more positive when zero leakage current is detected, the depletion mode GaN transistor can be adjusted to have an acceptable or even zero leakage current, a high reaction rate and an optimized efficiency.

    Control of semiconductor devices
    2.
    发明授权
    Control of semiconductor devices 有权

    公开(公告)号：US11831311B2

    公开(公告)日：2023-11-28

    申请号：US17536637

    申请日：2021-11-29

    申请人： Cirrus Logic International Semiconductor Ltd.

    发明人： John Laurence Pennock ,  John Paul Lesso

    IPC分类号： H03K19/0948 ,  H03K17/16 ,  H03K19/003 ,  H03M1/00

    CPC分类号： H03K19/0948 ,  H03K17/161 ,  H03K19/00346 ,  H03K19/00369 ,  H03M1/001

    摘要： This application relates to control of semiconductor devices, in particular MOS devices, so as to reduce RTS/flicker noise. A circuit (100) includes a first MOS device (103, 104) and a bias controller (107). The circuit is operable in at least a first circuit state (PRO) in which the first MOS device is active to contribute to a first signal (Sout) and a second circuit state (PRST) in which the first MOS device does not contribute to the first signal. The bias controller is operable to control voltages at one or more terminals of the first MOS device to apply a pre-bias (VPB1, VPB2) during an instance of the second circuit state. The pre-bias is applied to set an occupancy state of charge carriers traps within the first MOS device, to limit noise during subsequent operation in the first circuit state. In embodiments, the bias controller is configured so that at least one parameter of the pre-bias is selectively variable in use based on one or more operating conditions.

    OUTPUT DRIVER USING FEEDBACK NETWORK FOR SLEW RATE REDUCTION AND ASSOCIATED OUTPUT DRIVING METHOD
    4.
    发明公开
    OUTPUT DRIVER USING FEEDBACK NETWORK FOR SLEW RATE REDUCTION AND ASSOCIATED OUTPUT DRIVING METHOD 审中-公开

    公开(公告)号：US20230238960A1

    公开(公告)日：2023-07-27

    申请号：US17868739

    申请日：2022-07-19

    申请人： Airoha Technology Corp.

    发明人： Huan-Sheng Chen

    IPC分类号： H03K19/003 ,  H03K19/00 ,  H03K19/0948

    CPC分类号： H03K19/00346 ,  H03K19/0005 ,  H03K19/0948

    摘要： An output driver includes a first pre-driver circuit, a first driver circuit, a second pre-driver circuit, a second driver circuit, and a feedback network. The first pre-driver circuit pre-drives a first data input signal to generate a first pre-driving output signal. The first driver circuit drives the first pre-driving output signal to generate a first data output signal. The second pre-driver circuit pre-drives a second data input signal to generate a second pre-driving output signal, wherein the first data input signal and the second data input signal are a differential input of the output driver. The second driver circuit drives the second pre-driving output signal to generate a second data output signal. The feedback network performs a latching operation upon the first pre-driving output signal and the second pre-driving output signal according to the first data output signal and the second data output signal.

    RINGING SUPPRESSION CIRCUIT
    6.
    发明申请
    RINGING SUPPRESSION CIRCUIT 审中-公开

    公开(公告)号：US20180248542A1

    公开(公告)日：2018-08-30

    申请号：US15753596

    申请日：2016-08-25

    申请人： DENSO CORPORATION ,  SOKEN, INC.

    发明人： Hiroyuki MORI ,  Takuya HONDA ,  Tomohisa KISHIGAMI ,  Hirofumi ISOMURA

    IPC分类号： H03K5/1252 ,  H03K17/687 ,  H04B3/42

    CPC分类号： H03K5/1252 ,  H03K5/08 ,  H03K17/163 ,  H03K17/687 ,  H03K19/00346 ,  H04B3/42

    摘要： A ringing suppression circuit includes: a single line switching element, which is driven by a voltage, that is connected between a pair of signal lines; a controller that detects a change in a level of the differential signal and turns on the single line switching element to lower an impedance between the pair of signal lines; a period detector that detects a length of a suppressing period indicated by a setting signal, which is an input; and a suppressing period storage that stores the length of the suppressing period which is detected by the period detector. In addition, the pair of signal lines includes a high potential signal line and a low potential signal line. Moreover, the controller turns on the single line switching element for only the suppressing period having the length, which is stored in the suppressing period storage.