摘要:
Methods and apparatus are provided for evaluating the throughput limit of a communication system, such as a network node or system. A throughput limit of a communication system is evaluated by receiving a request to allocate at least one connection of a given data type; obtaining an assigned weight for the at least one connection, wherein the assigned weight is based on the throughput limit and a processing limit indicating a throughput of the communication system for the given data type within a given time window; and determining whether to allocate the at least one connection of a given data type based on whether a sum of the assigned weights for each existing allocated connection for each data type exceeds the throughput limit. The assigned weight for a given data type can be subtracted from the sum upon receiving a request to de-allocate a connection.
摘要:
Methods and apparatus are provided for evaluating the throughput limit of a communication system, such as a network node or system. A throughput limit of a communication system is evaluated by receiving a request to allocate at least one connection of a given data type; obtaining an assigned weight for the at least one connection, wherein the assigned weight is based on the throughput limit and a processing limit indicating a throughput of the communication system for the given data type within a given time window; and determining whether to allocate the at least one connection of a given data type based on whether a sum of the assigned weights for each existing allocated connection for each data type exceeds the throughput limit. The assigned weight for a given data type can be subtracted from the sum upon receiving a request to de-allocate a connection.
摘要:
A packet, cell or other data segment received in a physical layer device from a link layer device via an interface bus is processed to determine a port address for the data segment in the physical layer device. The port address, which may be an MPHY address, is determined using a combination of a first address value obtained from a link layer address portion of the data segment and a second address value obtained from a payload portion of the data segment. The data segment is stored in a memory location identified by the port address. The memory location may comprise a particular queue of the physical layer device.
摘要:
A packet, cell or other data segment received in a physical layer device from a link layer device via an interface bus is processed to determine a port address for the data segment in the physical layer device. The port address, which may be an MPHY address, is determined using a combination of a first address value obtained from a link layer address portion of the data segment and a second address value obtained from a payload portion of the data segment. The data segment is stored in a memory location identified by the port address. The memory location may comprise a particular queue of the physical layer device.
摘要:
A multiple-tipped drumming tool has 2-4 sticks each with a throughhole, joined together by a connector which passes through the throughhole such that the sticks are rotatable with respect to one another and can produce different tones with a musical instrument. The sticks may be connected by spring metals instead of such a connector. Instead of the connector, a fiber member may be passed through the throughholes of the sticks, being wrapped around the sticks such that the sticks are flexibly joined together.
摘要:
AN ELECTRICAL WRENCH FOR TIGHTENING NUTS, HAVING PERIPHERAL RIBS, WITHIN A SWITCH BOX. THE WRENCH IS ADAPTED TO FIT WITHIN THE SWITCH BOD AND HAS A LEVER ACTUATED PAWL FOR ENGAGING THE RIBS OF THE NUT. A RATCHET-LIKE MOTION WITHIN A LIMITED ARC WILL CAUSE THE PAWL TO ALTERNATELY CONTACT THE RIBS AND THEREBY CAUSE THE NUT TO BE TIGHTENED. AN INTERCHANGEABLE SOCKET IS UTILIZED TO POSITION THE WRENCH AND THE PAWL RELATIVE TO THE NUT.
摘要:
Methods and apparatus are provided for modeling signal delays in a metastability protection circuit. A metastability protection circuit that processes a signal that crosses between two clock domains is modeled by introducing a random transition delay into the signal upon detection of an edge in the signal. Thereafter, an effect of the random transition delay on one or more downstream logic elements can be evaluated. The random transition delay simulates a timing effect of a metastable state. The random transition delay can optionally be introduced only during a simulation stage of the metastability protection circuit. For example, the metastability protection circuit can be defined using a Register Transfer Language and the Register Transfer Language includes one or more statements that selectively allow the introducing step.