公开(公告)号：US5621758A

公开(公告)日：1997-04-15

申请号：US591718

申请日：1996-01-25

申请人： Shinichi Suzuki ,  Hirofumi Yamazoe

发明人： Shinichi Suzuki ,  Hirofumi Yamazoe

IPC分类号： H03M5/08 ,  H04L1/24 ,  H04L25/48 ,  H04L25/49 ,  H03K9/08

CPC分类号： H04L1/246 ,  H03M5/08 ,  H04L25/4902

摘要： A data output portion transmits a pulse signal having a pulse width according to a value of transmit data on a predetermined cycle. An H pulse width counter and an L pulse width counter measure a length of a high level period and a length of a low level period in the received pulse signal by using a clock signal having the same frequency as that of the clock signal used in the data output portion. A comparing portion compares the sum of both the measured lengths of the periods with the predetermined cycle, and outputs an error signal in case of a mismatch. In a PWM communication system, it is also possible to detect a signal delay or an error of the clock signal, which is temporarily caused within one cycle.

摘要翻译： 数据输出部分以预定的周期发送具有根据发送数据的值的脉冲宽度的脉冲信号。 H脉冲宽度计数器和L脉冲宽度计数器通过使用具有与在所述时钟信号中使用的时钟信号相同的频率的时钟信号来测量所接收的脉冲信号中的高电平周期的长度和低电平周期的长度 数据输出部分。 比较部分将测量的周期长度与预定周期进行比较，并且在不匹配的情况下输出误差信号。 在PWM通信系统中，也可以检测在一个周期内暂时引起的时钟信号的信号延迟或误差。

公开(公告)号：US06163851A

公开(公告)日：2000-12-19

申请号：US48995

申请日：1998-03-27

申请人： Hirofumi Yamazoe ,  Shinichi Suzuki

发明人： Hirofumi Yamazoe ,  Shinichi Suzuki

IPC分类号： G06F1/04 ,  G06F1/06 ,  G06F1/32

CPC分类号： G06F1/3228 ,  G06F1/06

摘要： A data processor including an alternative clock generator for generating, in a power saving mode, an alternative clock signal which is supplied to a peripheral circuit instead of a system clock signal. This enables only the peripheral circuit such as an A/D converter to be put into operation in response to the alternative clock signal in the power saving mode. This solves a problem of a conventional data processor in that it cannot achieve the power saving efficiently because it is unavoidable for the remaining portion of the conventional data processor like a CPU to be involved in a high-rate operation along with the peripheral circuit even if it is desired to operate only the peripheral circuit at a high-rate when releasing the sleep mode or changing the sleep mode to a high-rate mode.

摘要翻译： 一种数据处理器，包括备用时钟发生器，用于在功率节省模式下产生提供给外围电路而不是系统时钟信号的替代时钟信号。 这使得仅在诸如A / D转换器的外围电路响应于省电模式中的替代时钟信号而投入运行。 这解决了传统数据处理器的问题，因为它不能有效地实现功率节省，因为像CPU那样的常规数据处理器的其余部分不可避免地与外围电路一起参与高速率操作，即使 期望在释放睡眠模式或将睡眠模式改变为高速率模式时以高速率操作外围电路。