公开(公告)号：US08309458B2

公开(公告)日：2012-11-13

申请号：US13079941

申请日：2011-04-05

申请人： Keun-bong Lee

发明人： Keun-bong Lee

IPC分类号： H01L21/4763

CPC分类号： H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprises an electrical contact designed to reduce a contact resistance. The electrical contact has a size that varies according to a length of a region where the contact is to be formed.

摘要翻译： 半导体器件包括被设计成减小接触电阻的电接触。 电触点具有根据要形成触点的区域的长度而变化的尺寸。

公开(公告)号：US20110266698A1

公开(公告)日：2011-11-03

申请号：US13079941

申请日：2011-04-05

申请人： Keun-bong LEE

发明人： Keun-bong LEE

IPC分类号： H01L23/528 ,  H01L21/283

CPC分类号： H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprises an electrical contact designed to reduce a contact resistance. The electrical contact has a size that varies according to a length of a region where the contact is to be formed.

摘要翻译： 半导体器件包括被设计成减小接触电阻的电接触。 电触点具有根据要形成触点的区域的长度而变化的尺寸。

公开(公告)号：US20080123244A1

公开(公告)日：2008-05-29

申请号：US11983991

申请日：2007-11-13

申请人： Keun-Bong Lee ,  Jung-Hyeon Kim

发明人： Keun-Bong Lee ,  Jung-Hyeon Kim

IPC分类号： H01G4/005

CPC分类号： H01G4/005 ,  H01G4/012 ,  H01G4/30 ,  Y10T29/435

摘要： In a capacitor structure and a method of manufacturing the capacitor structure, first and second conductive patterns are formed on a substrate. The first and second conductive patterns extend in a first direction. The first and second conductive patterns are alternately arranged to be spaced apart from one another in a second direction substantially perpendicular to the first direction. An insulating interlayer is formed on the substrate to cover the first and second conductive patterns. Third and fourth conductive patterns extending in a third direction lying at an angle of between about 0° and about 90° relative to the first direction are formed on the insulating interlayer. The third and fourth conductive patterns are alternately arranged to be spaced apart from one another in a fourth direction substantially perpendicular to the third direction.

摘要翻译： 在电容器结构和制造电容器结构的方法中，在基板上形成第一和第二导电图案。 第一和第二导电图案沿第一方向延伸。 第一和第二导电图案交替地布置成在基本上垂直于第一方向的第二方向上彼此间隔开。 在衬底上形成绝缘中间层以覆盖第一和第二导电图案。 在绝缘中间层上形成有相对于第一方向以约0°至约90°之间的角度在第三方向延伸的第三和第四导电图案。 第三和第四导电图案交替地布置成在基本上垂直于第三方向的第四方向上彼此间隔开。

公开(公告)号：US20120112311A1

公开(公告)日：2012-05-10

申请号：US13239437

申请日：2011-09-22

申请人： Yong Sang Cho ,  Dae Lim Kang ,  Sung Soo Kim ,  Jong Ik Nam ,  Keun Bong Lee ,  Hye-Won Shim

发明人： Yong Sang Cho ,  Dae Lim Kang ,  Sung Soo Kim ,  Jong Ik Nam ,  Keun Bong Lee ,  Hye-Won Shim

IPC分类号： H01L29/86

CPC分类号： H01L23/62 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrical fuse includes first and second active regions doped with respective first-type and second-type impurities that form a horizontal P/N junction, first and second spaced apart silicide layers on respective portions of the top surfaces of the first and second active regions, and first and second contacts on the respective top surfaces of the first and second silicide layers. When a first reverse voltage that is higher than a threshold voltage is applied to the electrical fuse through the first and second contacts, the P/N junction is broken down by a reverse current flowing between the first and second active regions so that the electrical fuse is rendered conductive in response to a second reverse voltage that is less than the threshold voltage.

摘要翻译： 电熔丝包括掺杂有形成水平P / N结的各自的第一和第二类型杂质的第一和第二有源区，在第一和第二有源区的顶表面的相应部分上的第一和第二间隔开的硅化物层 以及在第一和第二硅化物层的相应顶表面上的第一和第二接触。 当高于阈值电压的第一反向电压通过第一和第二触点施加到电熔丝时，P / N结被在第一和第二有源区之间流动的反向电流分解，使得电熔丝 响应于小于阈值电压的第二反向电压而导通。

公开(公告)号：US20080122033A1

公开(公告)日：2008-05-29

申请号：US11986896

申请日：2007-11-27

申请人： Keun-Bong Lee ,  Jung-Hyeon Kim

发明人： Keun-Bong Lee ,  Jung-Hyeon Kim

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor device and a method of manufacturing the semiconductor device, an electric element is formed. A first insulation interlayer is formed on the electric element. A capacitor structure is formed on the first insulation interlayer. The capacitor structure vertically disposed relative to the electric element. The capacitor structure has a shape extending horizontally. Thus, a space under the capacitor structure having a relatively large area can be utilized for increasing an integration degree of the semiconductor device. Accordingly, the size of a semiconductor chip including the semiconductor device can be reduced.

摘要翻译： 在半导体器件和半导体器件的制造方法中，形成电子元件。 在电气元件上形成第一绝缘中间层。 在第一绝缘中间层上形成电容器结构。 电容器结构相对于电气元件垂直设置。 电容器结构具有水平延伸的形状。 因此，可以利用具有相对较大面积的电容器结构下面的空间来增加半导体器件的集成度。 因此，可以减少包括半导体器件的半导体芯片的尺寸。

公开(公告)号：US07869188B2

公开(公告)日：2011-01-11

申请号：US11998132

申请日：2007-11-28

申请人： Keun-Bong Lee ,  Jung-Hyeon Kim

发明人： Keun-Bong Lee ,  Jung-Hyeon Kim

IPC分类号： H01G4/005 ,  H01G4/06

CPC分类号： H01G4/012 ,  H01G4/005 ,  H01G4/236 ,  H01G4/30

摘要： A capacitor structure includes an insulating layer, first conductive patterns, second conductive patterns, an insulating interlayer, third conductive patterns, and fourth conductive patterns. The first and second conductive patterns are alternately arranged on the insulating layer to be spaced apart from one another. The first and second conductive patterns have side faces where concave portions and convex portions are formed. The insulating interlayer is formed on the insulating layer to cover the first and second conductive patterns. The third and fourth conductive patterns are alternately arranged on the insulating interlayer to be spaced apart from one another. The third and fourth conductive patterns have side faces where concave portions and convex portions are formed.

摘要翻译： 电容器结构包括绝缘层，第一导电图案，第二导电图案，绝缘夹层，第三导电图案和第四导电图案。 第一和第二导电图案交替地布置在绝缘层上以彼此间隔开。 第一和第二导电图案具有形成凹部和凸部的侧面。 在绝缘层上形成绝缘中间层以覆盖第一和第二导电图案。 第三和第四导电图案交替地布置在绝缘中间层上以彼此间隔开。 第三和第四导电图案具有形成凹部和凸部的侧面。

公开(公告)号：US07778008B2

公开(公告)日：2010-08-17

申请号：US11983991

申请日：2007-11-13

申请人： Keun-Bong Lee ,  Jung-Hyeon Kim

发明人： Keun-Bong Lee ,  Jung-Hyeon Kim

IPC分类号： H01G4/005 ,  H01G4/06

CPC分类号： H01G4/005 ,  H01G4/012 ,  H01G4/30 ,  Y10T29/435

摘要： In a capacitor structure and a method of manufacturing the capacitor structure, first and second conductive patterns are formed on a substrate. The first and second conductive patterns extend in a first direction. The first and second conductive patterns are alternately arranged to be spaced apart from one another in a second direction substantially perpendicular to the first direction. An insulating interlayer is formed on the substrate to cover the first and second conductive patterns. Third and fourth conductive patterns extending in a third direction lying at an angle of between about 0° and about 90° relative to the first direction are formed on the insulating interlayer. The third and fourth conductive patterns are alternately arranged to be spaced apart from one another in a fourth direction substantially perpendicular to the third direction.

摘要翻译： 在电容器结构和制造电容器结构的方法中，在基板上形成第一和第二导电图案。 第一和第二导电图案沿第一方向延伸。 第一和第二导电图案交替地布置成在基本上垂直于第一方向的第二方向上彼此间隔开。 在衬底上形成绝缘中间层以覆盖第一和第二导电图案。 在绝缘中间层上形成有相对于第一方向以约0°至约90°之间的角度在第三方向延伸的第三和第四导电图案。 第三和第四导电图案交替地布置成在基本上垂直于第三方向的第四方向上彼此间隔开。

公开(公告)号：US20080123245A1

公开(公告)日：2008-05-29

申请号：US11998132

申请日：2007-11-28

申请人： Keun-Bong Lee ,  Jung-Hyeon Kim

发明人： Keun-Bong Lee ,  Jung-Hyeon Kim

IPC分类号： H01G4/012

CPC分类号： H01G4/012 ,  H01G4/005 ,  H01G4/236 ,  H01G4/30

摘要： A capacitor structure includes an insulating layer, first conductive patterns, second conductive patterns, an insulating interlayer, third conductive patterns, and fourth conductive patterns. The first and second conductive patterns are alternately arranged on the insulating layer to be spaced apart from one another. The first and second conductive patterns have side faces where concave portions and convex portions are formed. The insulating interlayer is formed on the insulating layer to cover the first and second conductive patterns. The third and fourth conductive patterns are alternately arranged on the insulating interlayer to be spaced apart from one another. The third and fourth conductive patterns have side faces where concave portions and convex portions are formed.

摘要翻译： 电容器结构包括绝缘层，第一导电图案，第二导电图案，绝缘夹层，第三导电图案和第四导电图案。 第一和第二导电图案交替地布置在绝缘层上以彼此间隔开。 第一和第二导电图案具有形成凹部和凸部的侧面。 在绝缘层上形成绝缘中间层以覆盖第一和第二导电图案。 第三和第四导电图案交替地布置在绝缘中间层上以彼此间隔开。 第三和第四导电图案具有形成凹部和凸部的侧面。