公开(公告)号：US12170340B1

公开(公告)日：2024-12-17

申请号：US18614439

申请日：2024-03-22

Applicant: Diodes Incorporated

Inventor： Tao Long ,  Ze Rui Chen ,  Pin-Hao Huang ,  Paul Keith Gurry ,  Li-Hsien Chou

IPC: H01L21/308 ,  H01L21/768 ,  H01L21/8232 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/16 ,  H01L29/423 ,  H01L29/86

Abstract: A semiconductor rectifier device comprises: an epitaxial layer having a top surface and a bottom surface; a first trench comprising a first side wall, a second side wall, and a first bottom surface; a second trench adjacent to the first trench, the second trench comprising a third side wall, a fourth side wall, and a second bottom surface; a first doped region abutting against the first side wall and at least a part of the first bottom surface of the first trench; a second doped region adjacent to and separated from the first doped region, wherein the second doped region abuts against the third side wall, the fourth side wall and the second bottom surface of the second trench; a gate structure disposed on the top surface between the first trench and the second trench; and a contact metal layer disposed on the top surface of the epitaxial layer.

公开(公告)号：US12027611B2

公开(公告)日：2024-07-02

申请号：US17470692

申请日：2021-09-09

Applicant: Kabushiki Kaisha Toshiba ,  Toshiba Electronic Devices & Storage Corporation

Inventor： Yoko Iwakaji ,  Tomoko Matsudai

IPC: H01L29/739 ,  H01L29/86 ,  H01L29/861

CPC classification number: H01L29/7397 ,  H01L29/861

Abstract: A semiconductor device includes: a first electrode; a first semiconductor layer located on the first electrode in a diode region; a second semiconductor layer located on the first electrode in an IGBT region; a third semiconductor layer located in the diode region, the boundary region, and the IGBT region and positioned on the first semiconductor layer and the second semiconductor layer; a fourth semiconductor layer located on the third semiconductor layer in the boundary region and the IGBT region; a fifth semiconductor layer located on the third semiconductor layer and the fourth semiconductor layer; a second electrode located in the diode region; a third electrode located in the IGBT region; and a fourth electrode extending from an upper surface of the fifth semiconductor layer toward the third semiconductor layer in the boundary region and electrically insulated from the third electrode.

公开(公告)号：US12002890B2

公开(公告)日：2024-06-04

申请号：US17585284

申请日：2022-01-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehyun Yoo ,  Kyuok Lee ,  Uihui Kwon ,  Junhyeok Kim ,  Yongwoo Jeon ,  Dawon Jeong ,  Jaehyok Ko

IPC: H01L29/86 ,  H01L29/06 ,  H01L29/40 ,  H01L29/861

CPC classification number: H01L29/861 ,  H01L29/0634 ,  H01L29/404 ,  H01L29/0649

Abstract: A semiconductor protection device includes: an N-type epitaxial layer, a device isolation layer disposed in the N-type epitaxial layer, an N-type drift region disposed below the device isolation layer, an N-type well disposed in the N-type drift region, first and second P-type drift regions, respectively disposed to be in contact with the device isolation layer, and spaced apart from the N-type drift region, first and second P-type doped regions, respectively disposed in the first and second P-type drift regions, first and second N-type floating wells, respectively disposed in the first and second P-type drift regions to be spaced apart from the first and second P-type doped regions, and disposed to be in contact with the device isolation layer, and first and second contact layer, respectively disposed to cover the first and second N-type floating well, to be in contact with the device isolation layer.

公开(公告)号：US11984514B2

公开(公告)日：2024-05-14

申请号：US18324638

申请日：2023-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong Heo ,  Taehwan Moon ,  Hagyoul Bae ,  Seunggeol Nam ,  Sangwook Kim ,  Kwanghee Lee

IPC: H01L29/86 ,  H10B69/00 ,  H10K10/50 ,  H10K19/00

CPC classification number: H01L29/86 ,  H10B69/00 ,  H10K10/50 ,  H10K19/00 ,  H10K19/201

Abstract: A semiconductor apparatus includes a plurality of semiconductor devices. The semiconductor devices each include a ferroelectric layer, a conductive metal oxide layer, and a semiconductor layer, between two electrodes. The conductive metal oxide layer may be between the ferroelectric layer and the semiconductor layer. The ferroelectric layer, the conductive metal oxide layer, and the semiconductor layer may all include a metal oxide. The conductive metal oxide layer may include one or more materials selected from the group consisting of an indium oxide, a zinc oxide, a tin oxide, and any combination thereof.

公开(公告)号：US11973146B2

公开(公告)日：2024-04-30

申请号：US17771134

申请日：2020-10-27

Applicant: KABUSHIKI KAISHA TOKAI-RIKA-DENKI-SEISAKUSHO

Inventor： Kengo Shima ,  Yoshikazu Kataoka ,  Kazuya Adachi ,  Yuto Hakamata

IPC: H01L29/86 ,  H01L27/12 ,  H01L29/06 ,  H01L29/78 ,  H01L29/786 ,  H01L29/861

CPC classification number: H01L29/8611 ,  H01L27/1203 ,  H01L29/0657 ,  H01L29/7838 ,  H01L29/78603

Abstract: A semiconductor integrated circuit including: a substrate of a first conductivity type; a buried insulating film provided on the substrate; an active layer of the first conductivity type provided on the buried insulating film; a first impurity region of a second conductivity type formed within the active layer; an electric field relaxation layer of the second conductivity type formed within the active layer and surrounding the first impurity region; a second impurity region of the first conductivity type formed within the active layer and surrounding the electric field relaxation layer; and a groove formed surrounding the second impurity region and reaching the buried insulating film.

公开(公告)号：US20240128189A1

公开(公告)日：2024-04-18

申请号：US17968707

申请日：2022-10-18

Applicant: Micron Technology, Inc.

Inventor： Christopher G. Wieduwilt ,  James S. Rehmeyer

IPC: H01L23/528 ,  H01L27/112 ,  H01L29/86

CPC classification number: H01L23/528 ,  H01L27/11206 ,  H01L29/86 ,  H01L23/53209

Abstract: An antifuse device, including a gate having a gate dielectric layer; a first doping region connected to a first end of the gate; a second doping region connected to a second end of the gate, the second end being opposite to the first end of the gate; a channel that is disposed under the gate and that connects the first doping region and the second doping region; and an interconnection jumper that electrically connects the first doping region and the second doping region.

公开(公告)号：US11251307B2

公开(公告)日：2022-02-15

申请号：US16120705

申请日：2018-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-jin Park ,  Jin-bum Kim ,  Bong-soo Kim ,  Kyu-pil Lee ,  Hyeong-sun Hong ,  Yoo-sang Hwang

IPC: H01L29/786 ,  H01L29/778 ,  H01L29/88 ,  H01L21/02 ,  H01L29/06 ,  H01L29/16 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/86 ,  H01L29/24

Abstract: A device includes a substrate, a first electrode on the substrate, an insulating pattern on the substrate, a second electrode on an upper end of the insulating pattern, a two-dimensional (2D) material layer on a side surface of the insulating pattern, a gate insulating layer covering the 2D material layer, and a gate electrode contacting the gate insulting layer. The insulating pattern extends from the first electrode in a direction substantially vertical to the substrate. The 2D material layer includes at least one atomic layer of a 2D material that is substantially parallel to the side surface of the insulating pattern.

公开(公告)号：US11069770B2

公开(公告)日：2021-07-20

申请号：US16450351

申请日：2019-06-24

Applicant: Power Semiconductor

Inventor： Hamza Yilmaz

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/86 ,  H01L29/73 ,  H01L29/861 ,  H01L29/739

Abstract: Semiconductor devices and methods of fabrication are provided. The semiconductor device includes a Charge Injection Controlled (CIC) Fast Recovery Diode (FRD) to control charge injection by lowering carrier storage. The device can have a first conductivity type semiconductor substrate, and a drift region that includes a doped buffer region, a doped middle region and a doped field stop region or carrier storage region. The device can also include a second conductivity type shield region including a deep junction encircling (or substantially laterally beneath) the buffer region and a second conductivity type shallow junction anode region in electrical contact with a second conductivity type anode electrode. The deep junction can have a range of doping concentrations surrounding the buffer regions to deplete buffer charge laterally as well as vertically to prevent premature device breakdown. The first conductivity type may be N type and the second conductivity type may be P type.

公开(公告)号：US10790461B2

公开(公告)日：2020-09-29

申请号：US16462447

申请日：2017-11-16

Applicant: TORAY INDUSTRIES, INC.

Inventor： Daisuke Sakii ,  Seiichiro Murase ,  Junji Wakita

IPC: H01L29/86 ,  H01L51/05 ,  G06K19/07 ,  H01L51/00 ,  H01L51/10

Abstract: A field-effect transistor includes: a substrate; a source electrode; a drain electrode; a gate electrode; a semiconductor layer in contact with the source electrode and with the drain electrode; and a gate insulating layer insulating between the semiconductor layer and the gate electrode. The gate insulating layer comprising at least a polysiloxane having a structural unit represented by a general formula (1): in the general formula (1), R1 represents a hydrogen atom, an alkyl group, a cycloalkyl group, a heterocyclic group, an aryl group, a heteroaryl group, or an alkenyl group; R2 represents a hydrogen atom, an alkyl group, a cycloalkyl group, or a silyl group; m represents 0 or 1; A1 represents an organic group including at least two groups selected from a carboxy group, a sulfo group, a thiol group, a phenolic hydroxy group, or a derivative of these groups.

公开(公告)号：US10444275B2

公开(公告)日：2019-10-15

申请号：US15833331

申请日：2017-12-06

Applicant: Renesas Electronics Corporation

Inventor： Kenji Takeuchi

IPC: G01R31/02 ,  H01L29/86 ,  G01R31/26 ,  H01L29/739 ,  H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L29/06 ,  G01R1/20

Abstract: There are provided an electric-current sensing device capable of detecting an electric current with high accuracy, a load driving system, and a method for manufacturing the electric-current sensing device. According to one embodiment, the electric-current sensing device includes a sense IGBT through which an electric current proportional to an electric current flowing through a main IGBT flows. Further, a depth of a P type floating region from a lower end of each of a plurality of trench gates provided in the sense IGBT is shallower than a depth of another P type floating region from a lower end of each of a plurality of trench gates provided in the main IGBT.