公开(公告)号：US07696774B2

公开(公告)日：2010-04-13

申请号：US12123972

申请日：2008-05-20

申请人： Maryam Ashouei ,  Adit D. Singh ,  Abhijit Chatterjee

发明人： Maryam Ashouei ,  Adit D. Singh ,  Abhijit Chatterjee

IPC分类号： H03K19/003

CPC分类号： H03K19/00392 ,  Y10T29/49002

摘要： The present invention describes systems and methods to provide defect-tolerant logic devices. An exemplary embodiment of the present invention provides a defect-tolerant logic device including a plurality of CMOS gates and at least one defective CMOS gate included within the plurality of CMOS gates. Additionally, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-NMOS transistor if a P-network of the at least one defective CMOS gate is diagnosed as defective. Furthermore, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-PMOS transistor if the N-network of the at least one defective CMOS gate is diagnosed as defective.

摘要翻译： 本发明描述了提供容错逻辑器件的系统和方法。 本发明的示例性实施例提供了一种缺陷容限逻辑器件，其包括多个CMOS栅极和包括在多个CMOS栅极内的至少一个缺陷CMOS栅极。 另外，如果至少一个有缺陷的CMOS栅极的P网络被诊断为有缺陷的，则至少一个有缺陷的CMOS栅极能够被重新配置成伪NMOS晶体管。 此外，如果至少一个有缺陷的CMOS栅极的N网络被诊断为有缺陷的，则至少一个有缺陷的CMOS栅极能够被重新配置成伪PMOS晶体管。

公开(公告)号：US08462572B2

公开(公告)日：2013-06-11

申请号：US13231706

申请日：2011-09-13

申请人： Vibhu Sharma ,  Stefan Cosemans ,  Wim Dehaene ,  Francky Catthoor ,  Maryam Ashouei ,  Jos Huisken

发明人： Vibhu Sharma ,  Stefan Cosemans ,  Wim Dehaene ,  Francky Catthoor ,  Maryam Ashouei ,  Jos Huisken

IPC分类号： G11C7/02 ,  G11C7/00 ,  H03F3/45

CPC分类号： G11C11/413 ,  G11C7/06 ,  G11C7/065 ,  G11C7/08

摘要： An ultra low power sense amplifier circuit for amplifying a low swing input signal to a full swing output signal is disclosed. In one aspect, the amplifier circuit includes a first amplifier stage for pre-amplifying the input signal to an intermediate signal on its internal nodes, a second amplifier stage for amplifying the intermediate signal to the output signal, and a control circuit for sequentially activating the first and second amplifier. The first amplifier has a capacitor for limiting energy consumption and two upsized PMOS transistors without NMOS transistors.

摘要翻译： 公开了一种用于将低摆幅输入信号放大到全摆幅输出信号的超低功率读出放大器电路。 在一个方面，放大器电路包括用于将输入信号预放大到其内部节点上的中间信号的第一放大器级，用于将中间信号放大到输出信号的第二放大器级，以及用于依次激活 第一和第二放大器。 第一放大器具有用于限制能量消耗的电容器和没有NMOS晶体管的两个升压PMOS晶体管。

公开(公告)号：US20090289657A1

公开(公告)日：2009-11-26

申请号：US12123972

申请日：2008-05-20

申请人： Maryam Ashouei ,  Adit D. Singh ,  Abhijit Chatterjee

发明人： Maryam Ashouei ,  Adit D. Singh ,  Abhijit Chatterjee

IPC分类号： H03K19/003 ,  H01S4/00

CPC分类号： H03K19/00392 ,  Y10T29/49002

摘要： The present invention describes systems and methods to provide defect-tolerant logic devices. An exemplary embodiment of the present invention provides a defect-tolerant logic device including a plurality of CMOS gates and at least one defective CMOS gate included within the plurality of CMOS gates. Additionally, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-NMOS transistor if a P-network of the at least one defective CMOS gate is diagnosed as defective. Furthermore, the at least one defective CMOS gate is enabled to be reconfigured into a pseudo-PMOS transistor if the N-network of the at least one defective CMOS gate is diagnosed as defective.

摘要翻译： 本发明描述了提供容错逻辑器件的系统和方法。 本发明的示例性实施例提供了一种缺陷容限逻辑器件，其包括多个CMOS栅极和包括在多个CMOS栅极内的至少一个缺陷CMOS栅极。 另外，如果至少一个有缺陷的CMOS栅极的P网络被诊断为有缺陷的，则至少一个有缺陷的CMOS栅极能够被重新配置成伪NMOS晶体管。 此外，如果至少一个有缺陷的CMOS栅极的N网络被诊断为有缺陷的，则至少一个有缺陷的CMOS栅极能够被重新配置成伪PMOS晶体管。

公开(公告)号：US20120063252A1

公开(公告)日：2012-03-15

申请号：US13231706

申请日：2011-09-13

申请人： Vibhu Sharma ,  Stefan Cosemans ,  Wim Dehaene ,  Francky Catthoor ,  Maryam Ashouei ,  Jos Huisken

发明人： Vibhu Sharma ,  Stefan Cosemans ,  Wim Dehaene ,  Francky Catthoor ,  Maryam Ashouei ,  Jos Huisken

IPC分类号： H03F3/45 ,  G11C7/02

CPC分类号： G11C11/413 ,  G11C7/06 ,  G11C7/065 ,  G11C7/08

摘要： An ultra low power sense amplifier circuit for amplifying a low swing input signal to a full swing output signal is disclosed. In one aspect, the amplifier circuit includes a first amplifier stage for pre-amplifying the input signal to an intermediate signal on its internal nodes, a second amplifier stage for amplifying the intermediate signal to the output signal, and a control circuit for sequentially activating the first and second amplifier. The first amplifier has a capacitor for limiting energy consumption and two upsized PMOS transistors without NMOS transistors.

摘要翻译： 公开了一种用于将低摆幅输入信号放大到全摆幅输出信号的超低功率读出放大器电路。 在一个方面，放大器电路包括用于将输入信号预放大到其内部节点上的中间信号的第一放大器级，用于将中间信号放大到输出信号的第二放大器级，以及用于依次激活 第一和第二放大器。 第一放大器具有用于限制能量消耗的电容器和没有NMOS晶体管的两个升压PMOS晶体管。

公开(公告)号：US20110305099A1

公开(公告)日：2011-12-15

申请号：US13105806

申请日：2011-05-11

申请人： Vibhu Sharma ,  Stefan Cosemans ,  Wim Dehaene ,  Francky Catthoor ,  Maryam Ashouei ,  Jos Huisken

发明人： Vibhu Sharma ,  Stefan Cosemans ,  Wim Dehaene ,  Francky Catthoor ,  Maryam Ashouei ,  Jos Huisken

IPC分类号： G11C7/12

CPC分类号： G11C11/419 ,  G11C7/12 ,  G11C7/18 ,  G11C2207/002

摘要： A semiconductor memory device is disclosed. In one aspect, the device includes memory blocks with memory cells connected to a local bit-line, each local bit-line being connectable to a global bit-line for memory readout. There are also pre-charging circuitry for pre-charging the bit-lines and a read buffer for discharging the global bit-line during a read operation. The local bit-lines are pre-charged to a predetermined first voltage substantially lower than the supply voltage (VDD) of the memory device. A segment buffer is provided between each local bit-line and an input node of the respective read buffer. The segment buffer activates the read buffer during the read operation upon occurrence of a discharge on the connected local bit-line.

摘要翻译： 公开了一种半导体存储器件。 在一个方面，该设备包括具有连接到本地位线的存储器单元的存储器块，每个局部位线可连接到全局位线用于存储器读出。 还存在用于对位线进行预充电的预充电电路和用于在读操作期间对全局位线进行放电的读缓冲器。 本地位线被预充电到基本上低于存储器件的电源电压（VDD）的预定的第一电压。 在每个本地位线和相应读缓冲器的输入节点之间提供段缓冲器。 在连接的本地位线上发生放电时，段缓冲器在读操作期间激活读缓冲器。