公开(公告)号：US08462572B2

公开(公告)日：2013-06-11

申请号：US13231706

申请日：2011-09-13

申请人： Vibhu Sharma ,  Stefan Cosemans ,  Wim Dehaene ,  Francky Catthoor ,  Maryam Ashouei ,  Jos Huisken

发明人： Vibhu Sharma ,  Stefan Cosemans ,  Wim Dehaene ,  Francky Catthoor ,  Maryam Ashouei ,  Jos Huisken

IPC分类号： G11C7/02 ,  G11C7/00 ,  H03F3/45

CPC分类号： G11C11/413 ,  G11C7/06 ,  G11C7/065 ,  G11C7/08

摘要： An ultra low power sense amplifier circuit for amplifying a low swing input signal to a full swing output signal is disclosed. In one aspect, the amplifier circuit includes a first amplifier stage for pre-amplifying the input signal to an intermediate signal on its internal nodes, a second amplifier stage for amplifying the intermediate signal to the output signal, and a control circuit for sequentially activating the first and second amplifier. The first amplifier has a capacitor for limiting energy consumption and two upsized PMOS transistors without NMOS transistors.

摘要翻译： 公开了一种用于将低摆幅输入信号放大到全摆幅输出信号的超低功率读出放大器电路。 在一个方面，放大器电路包括用于将输入信号预放大到其内部节点上的中间信号的第一放大器级，用于将中间信号放大到输出信号的第二放大器级，以及用于依次激活 第一和第二放大器。 第一放大器具有用于限制能量消耗的电容器和没有NMOS晶体管的两个升压PMOS晶体管。

公开(公告)号：US20120063252A1

公开(公告)日：2012-03-15

申请号：US13231706

申请日：2011-09-13

申请人： Vibhu Sharma ,  Stefan Cosemans ,  Wim Dehaene ,  Francky Catthoor ,  Maryam Ashouei ,  Jos Huisken

发明人： Vibhu Sharma ,  Stefan Cosemans ,  Wim Dehaene ,  Francky Catthoor ,  Maryam Ashouei ,  Jos Huisken

IPC分类号： H03F3/45 ,  G11C7/02

CPC分类号： G11C11/413 ,  G11C7/06 ,  G11C7/065 ,  G11C7/08

摘要： An ultra low power sense amplifier circuit for amplifying a low swing input signal to a full swing output signal is disclosed. In one aspect, the amplifier circuit includes a first amplifier stage for pre-amplifying the input signal to an intermediate signal on its internal nodes, a second amplifier stage for amplifying the intermediate signal to the output signal, and a control circuit for sequentially activating the first and second amplifier. The first amplifier has a capacitor for limiting energy consumption and two upsized PMOS transistors without NMOS transistors.

摘要翻译： 公开了一种用于将低摆幅输入信号放大到全摆幅输出信号的超低功率读出放大器电路。 在一个方面，放大器电路包括用于将输入信号预放大到其内部节点上的中间信号的第一放大器级，用于将中间信号放大到输出信号的第二放大器级，以及用于依次激活 第一和第二放大器。 第一放大器具有用于限制能量消耗的电容器和没有NMOS晶体管的两个升压PMOS晶体管。

公开(公告)号：US20110305099A1

公开(公告)日：2011-12-15

申请号：US13105806

申请日：2011-05-11

申请人： Vibhu Sharma ,  Stefan Cosemans ,  Wim Dehaene ,  Francky Catthoor ,  Maryam Ashouei ,  Jos Huisken

发明人： Vibhu Sharma ,  Stefan Cosemans ,  Wim Dehaene ,  Francky Catthoor ,  Maryam Ashouei ,  Jos Huisken

IPC分类号： G11C7/12

CPC分类号： G11C11/419 ,  G11C7/12 ,  G11C7/18 ,  G11C2207/002

摘要： A semiconductor memory device is disclosed. In one aspect, the device includes memory blocks with memory cells connected to a local bit-line, each local bit-line being connectable to a global bit-line for memory readout. There are also pre-charging circuitry for pre-charging the bit-lines and a read buffer for discharging the global bit-line during a read operation. The local bit-lines are pre-charged to a predetermined first voltage substantially lower than the supply voltage (VDD) of the memory device. A segment buffer is provided between each local bit-line and an input node of the respective read buffer. The segment buffer activates the read buffer during the read operation upon occurrence of a discharge on the connected local bit-line.

摘要翻译： 公开了一种半导体存储器件。 在一个方面，该设备包括具有连接到本地位线的存储器单元的存储器块，每个局部位线可连接到全局位线用于存储器读出。 还存在用于对位线进行预充电的预充电电路和用于在读操作期间对全局位线进行放电的读缓冲器。 本地位线被预充电到基本上低于存储器件的电源电压（VDD）的预定的第一电压。 在每个本地位线和相应读缓冲器的输入节点之间提供段缓冲器。 在连接的本地位线上发生放电时，段缓冲器在读操作期间激活读缓冲器。

公开(公告)号：US20120063211A1

公开(公告)日：2012-03-15

申请号：US13231727

申请日：2011-09-13

申请人： Vibhu Sharma ,  Stefan Cosemans ,  Wim Dehaene ,  Francky Catthoor ,  Maryan Ashouei ,  Jos Huisken

发明人： Vibhu Sharma ,  Stefan Cosemans ,  Wim Dehaene ,  Francky Catthoor ,  Maryan Ashouei ,  Jos Huisken

IPC分类号： G11C11/00

CPC分类号： G11C11/413 ,  G11C7/06 ,  G11C7/065 ,  G11C7/08

摘要： A method for improving writability of an SRAM cell is disclosed. In one aspect, the method includes applying a first voltage higher than the global ground voltage and a third voltage higher than the global supply voltage to the ground supply nodes of the invertors of the SRAM cell, pre-charging one of the complementary bitlines to the global ground voltage, and applying a second voltage higher than the global supply voltage to the access transistors during a write operation to the SRAM cell.

摘要翻译： 公开了一种提高SRAM单元可写性的方法。 一方面，该方法包括将高于全局接地电压的第一电压和高于全局电源电压的第三电压施加到SRAM单元的反相器的接地电源节点，将互补位线之一预充电至 全局接地电压，并且在对SRAM单元的写入操作期间将高于全局电源电压的第二电压施加到存取晶体管。

公开(公告)号：US20110063934A1

公开(公告)日：2011-03-17

申请号：US12879972

申请日：2010-09-10

申请人： Vibhu Sharma ,  Stefan Cosemans ,  Wim Dehaene

发明人： Vibhu Sharma ,  Stefan Cosemans ,  Wim Dehaene

IPC分类号： G11C7/08

CPC分类号： G11C29/702 ,  G11C2207/2254

摘要： A memory circuit with multi-sized sense amplifier redundancy is disclosed. In one aspect, the circuit includes sense amplifiers connected to differential bit-lines and configured to amplify a voltage difference sensed on the differential bit-lines. The sense amplifiers include a first set of smaller sense amplifiers and a second set of larger sense amplifiers redundantly arranged to the first set to form redundant groups which each contain one smaller sense amplifiers and one larger sense amplifiers. The larger sense amplifiers have a failure rate lower than the smaller sense amplifiers. The circuit also includes calibration circuitry connected to enable and disable nodes of each of the sense amplifiers and configured to select for each redundant group either the smaller sense amplifier of the first set or, if the smaller sense amplifier fails, the larger sense amplifier of the second set.

摘要翻译： 公开了一种具有多尺寸读出放大器冗余的存储器电路。 在一个方面，电路包括连接到差分位线的读出放大器，并被配置为放大在差分位线上感测到的电压差。 读出放大器包括第一组较小读出放大器和第二组较大读出放大器，冗余布置到第一组以形成冗余组，每组包含一个较小的读出放大器和一个较大的读出放大器。 较大的感测放大器的故障率低于较小的感测放大器。 电路还包括校准电路，其连接到启用和禁用每个读出放大器的节点，并且被配置为为每个冗余组选择第一组的较小感测放大器，或者如果较小的读出放大器发生故障，则较大的读出放大器 第二集

公开(公告)号：US08576614B2

公开(公告)日：2013-11-05

申请号：US13587733

申请日：2012-08-16

申请人： Marc Heyns ,  Cedric Huyghebaert ,  Anne S. Verhulst ,  Daniele Leonelli ,  Rita Rooyackers ,  Wim Dehaene

发明人： Marc Heyns ,  Cedric Huyghebaert ,  Anne S. Verhulst ,  Daniele Leonelli ,  Rita Rooyackers ,  Wim Dehaene

IPC分类号： G11C11/00

CPC分类号： H01L29/7391 ,  B82Y10/00 ,  H01L27/11 ,  H01L27/11803 ,  H01L29/0657 ,  H01L29/66977 ,  H01L29/7831 ,  H01L29/78648 ,  H01L29/78684

摘要： A tunnel transistor is provided including a drain, a source and at least a first gate for controlling current between the drain and the source, wherein the first sides of respectively the first and the second gate dielectric material are positioned substantially along and substantially contact respectively the first and the second semiconductor part.

摘要翻译： 提供隧道晶体管，其包括漏极，源极和至少第一栅极，用于控制漏极和源极之间的电流，其中分别地第一和第二栅极电介质材料的第一侧基本上沿着并基本上接触 第一和第二半导体部件。

公开(公告)号：US20110068966A1

公开(公告)日：2011-03-24

申请号：US12954858

申请日：2010-11-27

申请人： Jorg Daniels ,  Wim Dehaene ,  Andreas Wiesbauer

发明人： Jorg Daniels ,  Wim Dehaene ,  Andreas Wiesbauer

IPC分类号： H03M1/38

CPC分类号： H03M1/1265 ,  G04F10/005 ,  H03M3/43 ,  H03M3/432 ,  H03M3/456 ,  H03M3/498

摘要： This disclosure relates to analog to digital conversion using irregular sampling. A method may include combining an analog signal with a feedback signal into a combined signal, filtering the combined signal using a digital noise shaping filter into a combined noise shaped signal, modulating the combined noise shaped signal into a modulated signal, generating samples of the modulated signal, and reconstructing as a digital signal the analog signal from the samples of the modulated signal.

摘要翻译： 本公开涉及使用不规则采样的模数转换。 一种方法可以包括将模拟信号与反馈信号组合成组合信号，使用数字噪声整形滤波器将组合信号滤波成组合的噪声整形信号，将组合的噪声整形信号调制成调制信号，产生调制信号的样本 信号，并将来自调制信号样本的模拟信号作为数字信号重建。

公开(公告)号：US20060014494A1

公开(公告)日：2006-01-19

申请号：US10532155

申请日：2003-10-21

申请人： Yves Vanderperren ,  Wim Dehaene

发明人： Yves Vanderperren ,  Wim Dehaene

IPC分类号： H04B1/00 ,  H04B1/10

CPC分类号： H04L27/2662 ,  H04L27/2657 ,  H04L27/2675

摘要： A receiver and a method for receiving a signal comprising a carrier modulated with a known training sequence is described in which an estimate a carrier frequency offset is obtained from an autocorrelation signal by autocorrelation of the part of the received signal containing a known training sequence. The received signal is compensated with the frequency offset obtained to form a compensated received signal, and a timing reference for the received signal is obtained by cross-correlation of the compensated received signal with a known training sequence.

摘要翻译： 描述了一种用于接收包括用已知训练序列调制的载波的信号的接收机和方法，其中通过对包含已知训练序列的接收信号的部分进行自相关，从自相关信号获得载波频率偏移的估计。 接收到的信号用获得的频率补偿补偿以形成补偿的接收信号，并且通过补偿的接收信号与已知训练序列的互相关来获得接收信号的定时参考。

公开(公告)号：US08081101B2

公开(公告)日：2011-12-20

申请号：US12701549

申请日：2010-02-06

申请人： Jorg Daniels ,  Wim Dehaene ,  Andreas Wiesbauer ,  Michiel Steyaert

发明人： Jorg Daniels ,  Wim Dehaene ,  Andreas Wiesbauer ,  Michiel Steyaert

IPC分类号： H03M1/60

CPC分类号： H03M1/1042 ,  H03M1/60

摘要： An apparatus is provided which has a first analog input and a second analog input. In a particular implementation, the first analog input is coupled to a first controllable oscillator and the second analog input is coupled to a second controllable oscillator. First and second digital output signals generated based on output oscillations from the first controllable oscillator and the second controllable oscillator are combined.

摘要翻译： 提供了一种具有第一模拟输入和第二模拟输入的装置。 在特定实现中，第一模拟输入耦合到第一可控振荡器，第二模拟输入耦合到第二可控振荡器。 基于来自第一可控振荡器和第二可控振荡器的输出振荡产生的第一和第二数字输出信号被组合。

公开(公告)号：US07696740B2

公开(公告)日：2010-04-13

申请号：US11972585

申请日：2008-01-10

申请人： Junfeng Zhou ,  Wim Dehaene

发明人： Junfeng Zhou ,  Wim Dehaene

IPC分类号： G05F1/40

CPC分类号： G05F1/56

摘要： A regulator circuit receives a power supply and provides a regulated power supply output suitable for integrated circuitry. It has a controllable current source circuit, a controller and a capacitor, such that an output of the controllable current source circuit can provide a lower frequency current part of the regulated power supply output, and the capacitor can supply a higher frequency current part of the regulated power supply output. The controllable current source circuit is controlled according to feedback from the regulated power supply output, and to restrict a rate of change of the output of the controllable current source circuit. The amount of EMI noise caused by high rate of change of current in power supply lines to the regulator circuit can be reduced. This can be done more efficiently or using a smaller capacitor than known arrangements.

摘要翻译： 调节器电路接收电源并提供适合于集成电路的稳压电源输出。 它具有可控电流源电路，控制器和电容器，使得可控电流源电路的输出可以提供稳压电源输出的较低频率电流部分，并且电容器可以提供更高频率的电流部分 稳压电源输出。 可控电流源电路根据来自稳压电源输出的反馈进行控制，并限制可控电流源电路输出的变化率。 可以减少由电源线向调节器电路的高电流变化引起的EMI噪声的量。 这可以比已知布置更有效地使用或使用较小的电容器。