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公开(公告)号：US08675341B2
公开(公告)日：2014-03-18
申请号：US13357677
申请日：2012-01-25
摘要： In a multilayer ceramic electronic component, when a region of a ceramic body in layers where neither of a first internal electrode and a second internal electrode is provided as viewed in a direction in which a plurality of ceramic layers are stacked on one another is defined as a non-effective layer region, a dummy lead-through conductor is arranged in the non-effective layer region so as to lead to at least two locations on portions of superficies of the ceramic body and be electrically connected to a second external electrode. When a conductive medium is brought into contact with one of a plurality of exposed edges of the dummy lead-through conductor, a current is also applied to the other exposed edges.
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公开(公告)号：US08654504B2
公开(公告)日：2014-02-18
申请号：US13561285
申请日：2012-07-30
摘要： In a monolithic ceramic electronic component, given that an interval between outer-layer dummy conductors adjacent to each other in an outer layer portion is d1, and that an interval between first and second inner electrodes adjacent to each other in an inner layer portion is d2, 1.7d2≦d1 is satisfied. By reducing a density of the outer-layer dummy conductors in the outer layer portion on that condition, pressing of the inner electrodes through the outer-layer dummy conductors is relieved in a pressing step before firing. As a result, a distance between the inner electrodes can be prevented from being locally shortened. It is hence possible to effectively reduce and prevent degradation of reliability of the monolithic ceramic electronic component, e.g., a reduction of BDV.
摘要翻译： 在单片陶瓷电子部件中，由于外层部分相邻的外层虚设导体之间的间隔为d1，内层部分相邻的第一内电极与第二内电极的间隔为d2 ，1.7d2@d1满足。 通过在该条件下减小外层部分中的外层虚设导体的密度，通过外层虚设导体按压内电极在烧制前的加压步骤中被释放。 结果，可以防止内部电极之间的距离局部缩短。 因此，可以有效地降低并防止单片陶瓷电子部件的可靠性的劣化，例如BDV的降低。
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公开(公告)号：US08599532B2
公开(公告)日：2013-12-03
申请号：US13517624
申请日：2012-06-14
申请人： Masahiro Sakuratani
发明人： Masahiro Sakuratani
IPC分类号： H01G4/228
摘要： In a monolithic ceramic electronic component, where a distance in the height direction between one of outer-layer dummy conductors in an outer layer portion, which is arranged closest to an inner layer portion, and one of inner electrodes in the inner layer portion, which is arranged closest to the outer layer portion, is b, and an opposing distance between an adjacent pair of first inner electrodes and second inner electrodes in the height direction is t, 2t≦b is satisfied, such that the outer-layer dummy conductors can be spaced a sufficient distance away from the inner electrodes, and such that the distance between the inner electrodes can be prevented from being reduced when the inner electrodes arranged in overlapping relation to the outer-layer dummy conductors are pressed in a pressing step before firing, and a reduction of BDV can be prevented.
摘要翻译： 在整体式陶瓷电子部件中，在外层部分的外层虚拟导体中的一个最靠近内层部分布置的高度方向与内层部分内部电极中的一个之间的高度方向上的距离， 布置成最靠近外层部分b，并且相邻的第一内部电极和第二内部电极在高度方向上的相对距离为t，满足2t @ b，使得外层虚拟导体可以 与内部电极隔开足够的距离，并且当在烧制之前的加压步骤中按压与外层虚拟导体重叠的内部电极时，可以防止内部电极之间的距离减小， 可以防止BDV的降低。
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公开(公告)号：US20120188684A1
公开(公告)日：2012-07-26
申请号：US13357677
申请日：2012-01-25
IPC分类号： H01G4/12
摘要： In a multilayer ceramic electronic component, when a region of a ceramic body in layers where neither of a first internal electrode and a second internal electrode is provided as viewed in a direction in which a plurality of ceramic layers are stacked on one another is defined as a non-effective layer region, a dummy lead-through conductor is arranged in the non-effective layer region so as to lead to at least two locations on portions of superficies of the ceramic body and be electrically connected to a second external electrode. When a conductive medium is brought into contact with one of a plurality of exposed edges of the dummy lead-through conductor, a current is also applied to the other exposed edges.
摘要翻译： 在多层陶瓷电子部件中，当在多个陶瓷层彼此堆叠的方向上观察时，当从堆叠多个陶瓷层的方向观察时，设置第一内部电极和第二内部电极两者的陶瓷体的区域被定义为 非有效层区域，虚设引线导体布置在非有效层区域中，以便导致陶瓷体的多个部分上的至少两个位置并且电连接到第二外部电极。 当导电介质与虚拟导通导体的多个暴露边缘中的一个接触时，电流也被施加到其它暴露边缘。
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5.发明授权Monolithic ceramic electronic component including outer-layer dummy electrode groups 有权单片陶瓷电子元件包括外层虚拟电极组公开(公告)号：US08797708B2
公开(公告)日：2014-08-05
申请号：US13517625
申请日：2012-06-14
IPC分类号： H01G4/005 , H01G4/06 , H01L41/047 , H01L41/273 , H01L41/29
CPC分类号： H01L41/0471 , H01L41/273 , H01L41/29
摘要： Two or more outer-layer dummy conductors are successively arranged at predetermined intervals in the height direction, thereby forming a plurality of outer-layer dummy groups. Given that an interval between the adjacent outer-layer dummy conductors within each of the outer-layer dummy groups is d and an interval between the adjacent outer-layer dummy groups is g, g is greater than d. On that condition, the outer-layer dummy groups can be positioned satisfactorily apart away from each other, while plating deposition points are ensured. As a result, pressing of inner electrodes through the outer-layer dummy conductors can be relieved, whereby the distance between the inner electrodes can be prevented from being locally shortened and a reduction of BDV can be prevented.
摘要翻译： 两个以上的外层虚设导体在高度方向上以规定的间隔相继配置，形成多个外层虚拟组。 假设每个外层虚拟组内的相邻外层虚拟导体之间的间隔为d，相邻外层虚拟组之间的间隔为g，则g大于d。 在这种情况下，可以将外层虚拟组放置得令人满意地分开，同时确保镀敷沉积点。 结果，可以减轻内部电极穿过外层虚拟导体的压力，从而可以防止内部电极之间的距离局部缩短并且可以防止BDV的降低。
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公开(公告)号：US08687344B2
公开(公告)日：2014-04-01
申请号：US13494042
申请日：2012-06-12
摘要： A laminated ceramic electronic component includes curved surface portions provided in an outer surface of a ceramic element assembly, and internal conductors provided within the ceramic element assembly that are exposed in the curved surface portions and principal surfaces to define starting points for plating deposition. A base layer, in an external conductor, which is defined by a plating film is arranged so as to directly cover the exposed portions of the internal conductors.
摘要翻译： 层叠陶瓷电子部件包括设置在陶瓷元件组件的外表面中的弯曲表面部分和设置在陶瓷元件组件内的内部导体，其暴露在弯曲表面部分和主表面中以限定电镀沉积的起始点。 在由镀膜限定的外部导体中的基底层被布置成直接覆盖内部导体的暴露部分。
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公开(公告)号：US20130033154A1
公开(公告)日：2013-02-07
申请号：US13561285
申请日：2012-07-30
IPC分类号： H01G4/30 , H01C7/13 , H01L41/047
摘要： In a monolithic ceramic electronic component, given that an interval between outer-layer dummy conductors adjacent to each other in an outer layer portion is d1, and that an interval between first and second inner electrodes adjacent to each other in an inner layer portion is d2, 1.7d2≦d1 is satisfied. By reducing a density of the outer-layer dummy conductors in the outer layer portion on that condition, pressing of the inner electrodes through the outer-layer dummy conductors is relieved in a pressing step before firing. As a result, a distance between the inner electrodes can be prevented from being locally shortened. It is hence possible to effectively reduce and prevent degradation of reliability of the monolithic ceramic electronic component, e.g., a reduction of BDV.
摘要翻译： 在单片陶瓷电子部件中，由于外层部分相邻的外层虚设导体之间的间隔为d1，内层部分相邻的第一内电极与第二内电极的间隔为d2 ，1.7d2＆nlE; d1。 通过在该条件下减小外层部分中的外层虚设导体的密度，通过外层虚设导体按压内电极在烧制前的加压步骤中被释放。 结果，可以防止内部电极之间的距离局部缩短。 因此，可以有效地降低并防止单片陶瓷电子部件的可靠性的劣化，例如BDV的降低。
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公开(公告)号：US20120320495A1
公开(公告)日：2012-12-20
申请号：US13494042
申请日：2012-06-12
IPC分类号： H01G4/12
摘要： A laminated ceramic electronic component includes curved surface portions provided in an outer surface of a ceramic element assembly, and internal conductors provided within the ceramic element assembly that are exposed in the curved surface portions and principal surfaces to define starting points for plating deposition. A base layer, in an external conductor, which is defined by a plating film is arranged so as to directly cover the exposed portions of the internal conductors.
摘要翻译： 层叠陶瓷电子部件包括设置在陶瓷元件组件的外表面中的弯曲表面部分和设置在陶瓷元件组件内的内部导体，其暴露在弯曲表面部分和主表面中以限定电镀沉积的起始点。 在由镀膜限定的外部导体中的基底层被布置成直接覆盖内部导体的暴露部分。
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公开(公告)号：US20120319537A1
公开(公告)日：2012-12-20
申请号：US13517625
申请日：2012-06-14
IPC分类号： H01L41/047 , H01C7/13 , H01G4/30
CPC分类号： H01L41/0471 , H01L41/273 , H01L41/29
摘要： Two or more outer-layer dummy conductors are successively arranged at predetermined intervals in the height direction, thereby forming a plurality of outer-layer dummy groups. Given that an interval between the adjacent outer-layer dummy conductors within each of the outer-layer dummy groups is d and an interval between the adjacent outer-layer dummy groups is g, g is greater than d. On that condition, the outer-layer dummy groups can be positioned satisfactorily apart away from each other, while plating deposition points are ensured. As a result, pressing of inner electrodes through the outer-layer dummy conductors can be relieved, whereby the distance between the inner electrodes can be prevented from being locally shortened and a reduction of BDV can be prevented.
摘要翻译： 两个以上的外层虚设导体在高度方向上以规定的间隔相继配置，形成多个外层虚拟组。 假设每个外层虚拟组内的相邻外层虚拟导体之间的间隔为d，相邻外层虚拟组之间的间隔为g，则g大于d。 在这种情况下，可以将外层虚拟组放置得令人满意地分开，同时确保镀敷沉积点。 结果，可以减轻内部电极穿过外层虚拟导体的压力，从而可以防止内部电极之间的距离局部缩短并且可以防止BDV的降低。
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公开(公告)号：US20120319536A1
公开(公告)日：2012-12-20
申请号：US13517624
申请日：2012-06-14
申请人： Masahiro SAKURATANI
发明人： Masahiro SAKURATANI
IPC分类号： H01L41/047 , H01C7/13 , H01G4/30
摘要： In a monolithic ceramic electronic component, where a distance in the height direction between one of outer-layer dummy conductors in an outer layer portion, which is arranged closest to an inner layer portion, and one of inner electrodes in the inner layer portion, which is arranged closest to the outer layer portion, is b, and an opposing distance between an adjacent pair of first inner electrodes and second inner electrodes in the height direction is t, 2t≦b is satisfied, such that the outer-layer dummy conductors can be spaced a sufficient distance away from the inner electrodes, and such that the distance between the inner electrodes can be prevented from being reduced when the inner electrodes arranged in overlapping relation to the outer-layer dummy conductors are pressed in a pressing step before firing, and a reduction of BDV can be prevented.
摘要翻译： 在整体式陶瓷电子部件中，在外层部分的外层虚拟导体中的一个最靠近内层部分布置的高度方向与内层部分内部电极中的一个之间的高度方向上的距离， 布置成最靠近外层部分b，并且相邻的一对第一内部电极和第二内部电极在高度方向上的相对距离为t，满足2t＆nlE; b，使得外部虚拟导体可以 与内部电极隔开足够的距离，并且当在烧制之前的加压步骤中按压与外层虚拟导体重叠的内部电极时，可以防止内部电极之间的距离减小， 可以防止BDV的降低。
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