STATE RETENTION POWER GATED CELL
    1.
    发明申请
    STATE RETENTION POWER GATED CELL 有权
    状态保持电力接通电池

    公开(公告)号:US20150091626A1

    公开(公告)日:2015-04-02

    申请号:US14277804

    申请日:2014-05-15

    IPC分类号: H03K3/012 H03K3/356 H03K19/00

    摘要: A state retention power gated cell includes a logic cell arranged in two or more rows. The logic cell has an active layer including at least a first well and a second well disposed in first and second rows, respectively. In a normal operation mode, the first well is powered with a first bias voltage, the second well is powered with a second bias voltage, the first power supply line is powered with VDDC, and the second power supply line is powered with VDD. In a standby mode, the first well preferably is powered down, the second well is powered with the second bias voltage, the first power supply line is powered with VDDC, and the second power supply line is powered down.

    摘要翻译: 状态保持功率选通单元包括布置成两行或多行的逻辑单元。 逻辑单元具有分别包括至少第一阱和第二阱的有源层,第一阱和第二阱分别布置在第一和第二行中。 在正常工作模式下,第一个阱由第一偏置电压供电,第二个阱由第二个偏置电压供电,第一个电源线由VDDC供电,第二个电源线由VDD供电。 在待机模式中,第一阱优选地断电,第二阱由第二偏置电压供电,第一电源线由VDDC供电,并且第二电源线断电。

    State retention power gated cell
    2.
    发明授权
    State retention power gated cell 有权
    状态保持力门控电池

    公开(公告)号:US08987786B1

    公开(公告)日:2015-03-24

    申请号:US14277804

    申请日:2014-05-15

    摘要: A state retention power gated cell includes a logic cell arranged in two or more rows. The logic cell has an active layer including at least a first well and a second well disposed in first and second rows, respectively. In a normal operation mode, the first well is powered with a first bias voltage, the second well is powered with a second bias voltage, the first power supply line is powered with VDDC, and the second power supply line is powered with VDD. In a standby mode, the first well preferably is powered down, the second well is powered with the second bias voltage, the first power supply line is powered with VDDC, and the second power supply line is powered down.

    摘要翻译: 状态保持功率选通单元包括布置成两行或多行的逻辑单元。 逻辑单元具有分别包括至少第一阱和第二阱的有源层,第一阱和第二阱分别布置在第一和第二行中。 在正常工作模式下,第一个阱由第一偏置电压供电,第二个阱由第二个偏置电压供电,第一个电源线由VDDC供电,第二个电源线由VDD供电。 在待机模式中,第一阱优选地断电,第二阱由第二偏置电压供电,第一电源线由VDDC供电,并且第二电源线断电。

    Electronic device with power mode control buffers
    3.
    发明授权
    Electronic device with power mode control buffers 有权
    带电源模式控制缓冲器的电子设备

    公开(公告)号:US08884669B2

    公开(公告)日:2014-11-11

    申请号:US13964110

    申请日:2013-08-12

    IPC分类号: H03L7/00 H03K19/00

    CPC分类号: H03K19/0016

    摘要: An electronic device has a power control module for causing selected functional blocks to run in a low power mode of operation, while leaving other functional blocks supplied continuously with power. A power mode control distribution network includes serially connected chains of buffers in a distribution tree for distributing power mode control signals received at a common input end to respective output ends which are connected to respective functional blocks. In the low power mode of operation the power control module causes power to be supplied continuously to output buffers at the output ends of the chains while causing power supplied to other buffers to be reduced or cut-off. The output buffers include feedback paths for causing the states of the output buffers prior to the low power mode of operation to latch during the low power mode of operation.

    摘要翻译: 电子设备具有功率控制模块,用于使所选择的功能块以低功率操作模式运行,同时留下连续供电的其他功能块。 功率模式控制分配网络包括分配树中的串行连接的缓冲器链,用于将在公共输入端接收的功率模式控制信号分配到连接到各个功能块的相应输出端。 在低功率操作模式下,功率控制模块连续供电以在链的输出端输出缓冲器,同时引起供应给其它缓冲器的功率减小或截止。 输出缓冲器包括用于在低功率操作模式之前使输出缓冲器的状态在低功率操作模式之前锁存的反馈路径。

    ELECTRONIC DEVICE WITH POWER MODE CONTROL BUFFERS
    4.
    发明申请
    ELECTRONIC DEVICE WITH POWER MODE CONTROL BUFFERS 有权
    具有电源模式控制缓冲器的电子设备

    公开(公告)号:US20140210523A1

    公开(公告)日:2014-07-31

    申请号:US13964110

    申请日:2013-08-12

    IPC分类号: H03K3/012

    CPC分类号: H03K19/0016

    摘要: An electronic device has a power control module for causing selected functional blocks to run in a low power mode of operation, while leaving other functional blocks supplied continuously with power. A power mode control distribution network includes serially connected chains of buffers in a distribution tree for distributing power mode control signals received at a common input end to respective output ends which are connected to respective functional blocks. In the low power mode of operation the power control module causes power to be supplied continuously to output buffers at the output ends of the chains while causing power supplied to other buffers to be reduced or cut-off. The output buffers include feedback paths for causing the states of the output buffers prior to the low power mode of operation to latch during the low power mode of operation.

    摘要翻译: 电子设备具有功率控制模块,用于使所选择的功能块以低功率操作模式运行,同时留下连续供电的其他功能块。 功率模式控制分配网络包括分配树中的串行连接的缓冲器链,用于将在公共输入端接收的功率模式控制信号分配到连接到各个功能块的相应输出端。 在低功率操作模式下,功率控制模块连续供电以在链的输出端输出缓冲器,同时引起供应给其它缓冲器的功率减小或截止。 输出缓冲器包括用于在低功率操作模式之前使输出缓冲器的状态在低功率操作模式之前锁存的反馈路径。