公开(公告)号：US08884669B2

公开(公告)日：2014-11-11

申请号：US13964110

申请日：2013-08-12

申请人： Xiaoxiang Geng ,  Zhihong Cheng ,  Huabin Du ,  Miaolin Tan

发明人： Xiaoxiang Geng ,  Zhihong Cheng ,  Huabin Du ,  Miaolin Tan

IPC分类号： H03L7/00 ,  H03K19/00

CPC分类号： H03K19/0016

摘要： An electronic device has a power control module for causing selected functional blocks to run in a low power mode of operation, while leaving other functional blocks supplied continuously with power. A power mode control distribution network includes serially connected chains of buffers in a distribution tree for distributing power mode control signals received at a common input end to respective output ends which are connected to respective functional blocks. In the low power mode of operation the power control module causes power to be supplied continuously to output buffers at the output ends of the chains while causing power supplied to other buffers to be reduced or cut-off. The output buffers include feedback paths for causing the states of the output buffers prior to the low power mode of operation to latch during the low power mode of operation.

摘要翻译： 电子设备具有功率控制模块，用于使所选择的功能块以低功率操作模式运行，同时留下连续供电的其他功能块。 功率模式控制分配网络包括分配树中的串行连接的缓冲器链，用于将在公共输入端接收的功率模式控制信号分配到连接到各个功能块的相应输出端。 在低功率操作模式下，功率控制模块连续供电以在链的输出端输出缓冲器，同时引起供应给其它缓冲器的功率减小或截止。 输出缓冲器包括用于在低功率操作模式之前使输出缓冲器的状态在低功率操作模式之前锁存的反馈路径。

公开(公告)号：US20140210523A1

公开(公告)日：2014-07-31

申请号：US13964110

申请日：2013-08-12

申请人： Xiaoxiang Geng ,  Zhihong Cheng ,  Huabin Du ,  Miaolin Tan

发明人： Xiaoxiang Geng ,  Zhihong Cheng ,  Huabin Du ,  Miaolin Tan

IPC分类号： H03K3/012

CPC分类号： H03K19/0016

摘要： An electronic device has a power control module for causing selected functional blocks to run in a low power mode of operation, while leaving other functional blocks supplied continuously with power. A power mode control distribution network includes serially connected chains of buffers in a distribution tree for distributing power mode control signals received at a common input end to respective output ends which are connected to respective functional blocks. In the low power mode of operation the power control module causes power to be supplied continuously to output buffers at the output ends of the chains while causing power supplied to other buffers to be reduced or cut-off. The output buffers include feedback paths for causing the states of the output buffers prior to the low power mode of operation to latch during the low power mode of operation.

摘要翻译： 电子设备具有功率控制模块，用于使所选择的功能块以低功率操作模式运行，同时留下连续供电的其他功能块。 功率模式控制分配网络包括分配树中的串行连接的缓冲器链，用于将在公共输入端接收的功率模式控制信号分配到连接到各个功能块的相应输出端。 在低功率操作模式下，功率控制模块连续供电以在链的输出端输出缓冲器，同时引起供应给其它缓冲器的功率减小或截止。 输出缓冲器包括用于在低功率操作模式之前使输出缓冲器的状态在低功率操作模式之前锁存的反馈路径。

公开(公告)号：US20150084680A1

公开(公告)日：2015-03-26

申请号：US14191403

申请日：2014-02-26

申请人： Zhihong Cheng ,  Zhijun Chen ,  Huabin Du ,  Peidong Wang ,  Shayan Zhang

发明人： Zhihong Cheng ,  Zhijun Chen ,  Huabin Du ,  Peidong Wang ,  Shayan Zhang

IPC分类号： H03K17/22

CPC分类号： G11C5/14

摘要： A state retention power gated (SRPG) cell includes a retention circuit coupled to a power gated circuit. The retention circuit stores state information of the power gated circuit before a low power period is started. A gated power supply coupled to the power gated circuit and to a first end of a power supply switch supplies a gated supply voltage to the power gated circuit during a non-low power period. A local power supply coupled to the retention circuit and to a second end of the power supply switch is coupled to the gated power supply in the non-low power period, and a non-gated power supply is coupled to the local power supply via an isolation element to isolate the non-gated power supply from the local power supply during the non-low power period, and to couple the non-gated power supply to the local power supply during the low power period.

摘要翻译： 状态保持功率门控（SRPG）单元包括耦合到电源门控电路的保持电路。 保持电路在开始低功率周期之前存储电源门控电路的状态信息。 耦合到电源门控电路和电源开关的第一端的门控电源在非低功率时段期间向门控电路提供门控电源电压。 耦合到保持电路和电源开关的第二端的局部电源在非低功率时段内耦合到门控电源，并且非门控电源经由 隔离元件，以在非低功率周期期间将非门控电源与本地电源隔离，并且在低功率周期期间将非门控电源耦合到本地电源。

公开(公告)号：US08601426B1

公开(公告)日：2013-12-03

申请号：US13717646

申请日：2012-12-17

申请人： Huabin Du

发明人： Huabin Du

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/78

摘要： A level shifter physical verification system identifies missing level shifters in a multi-voltage domain integrated circuit design. The system analyzes a physical layout design data file for design to identify domains and signals that cross domains, and connected nets of devices within the IC design having one or more missing level shifters.

摘要翻译： 电平移位器物理验证系统识别多电压域集成电路设计中的缺失电平移位器。 该系统分析用于设计的物理布局设计数据文件以识别跨域的域和信号，以及连接具有一个或多个缺失电平移位器的IC设计内的设备的网络。