公开(公告)号：US10540284B2

公开(公告)日：2020-01-21

申请号：US14445237

申请日：2014-07-29

申请人： Dirk Wendel ,  Oliver Bibel ,  Joachim Fader ,  Wilhard Christophorus Von Wendorff

发明人： Dirk Wendel ,  Oliver Bibel ,  Joachim Fader ,  Wilhard Christophorus Von Wendorff

IPC分类号： G06F12/0831 ,  G06F12/14 ,  G06F12/084 ,  G06F12/0811

摘要： A cache-coherent multiprocessor system comprising processing units, a shared memory resource accessible by the processing units, the shared memory resource being divided into at least one shared region, at least one first region, and at least one second region, a first cache, a second cache, a coherency unit, and a monitor unit, wherein the monitor unit is adapted to generate an error signal, when the coherency unit affects the at least one first region due to a memory access from the second processing unit and/or when the coherency unit affects the at least one second region due to a memory access from the first processing unit, and a method for detecting failures in a such a cache-coherent multiprocessor system.

公开(公告)号：US20160034398A1

公开(公告)日：2016-02-04

申请号：US14445237

申请日：2014-07-29

申请人： DIRK WENDEL ,  OLIVER BIBEL ,  JOACHIM FADER ,  WILHARD CHRISTOPHORUS VON WENDORFF

发明人： DIRK WENDEL ,  OLIVER BIBEL ,  JOACHIM FADER ,  WILHARD CHRISTOPHORUS VON WENDORFF

IPC分类号： G06F12/08

摘要： A cache-coherent multiprocessor system comprising processing units, a shared memory resource accessible by the processing units, the shared memory resource being divided into at least one shared region, at least one first region, and at least one second region, a first cache, a second cache, a coherency unit, and a monitor unit, wherein the monitor unit is adapted to generate an error signal, when the coherency unit affects the at least one first region due to a memory access from the second processing unit and/or when the coherency unit affects the at least one second region due to a memory access from the first processing unit, and a method for detecting failures in a such a cache-coherent multiprocessor system.

摘要翻译： 一种高速缓存一致的多处理器系统，包括处理单元，由处理单元可访问的共享存储器资源，共享存储器资源被划分为至少一个共享区域，至少一个第一区域和至少一个第二区域，第一高速缓存， 第二高速缓存，一致性单元和监视器单元，其中当所述一致性单元由于来自所述第二处理单元的存储器访问而影响所述至少一个第一区域时和/或何时所述监视单元适于产生错误信号 相关性单元由于来自第一处理单元的存储器访问而影响至少一个第二区域，以及用于检测这种高速缓存相关多处理器系统中的故障的方法。