摘要:
A method for detecting a freeze-frame condition comprises receiving a sequence of images from at least one digital device; selectively encoding a first subset of the sequence of images using a first coding scheme that causes an adjustment to an image characteristic of the selected images being encoded; selectively encoding a second subset of the sequence of images using a second coding scheme; storing the first encoded subset and second encoded subset; retrieving the stored first encoded subset and second encoded subset; selectively decoding the first subset of the selected images using the first coding scheme and selectively decoding the second subset of the selected images using the second coding scheme to re-create the sequence of images. A freeze-frame condition in the re-created sequence of images is identifiable based on a plurality of decoded images being different with respect to the image characteristic across multiple decoded image frames.
摘要:
The present application relates to a signal integrity module for validating one or more control signals in time domain and a method thereof. The one or more control signals are received via a signal input from at least one control signal generating unit. A new signature is generated by a signature generating unit on the basis of a current signature and the state of the one or more control signals at a watch point. The current signature is latched into a signature register upon receiving a trigger signal. The latched signature is representative of the time course of the one or more control signals at the watch point over a monitoring period defined by the trigger signal. The latched signature is compared by a signature comparator with a pre-calculated signature to validate the integrity of the one or more control signals with respect to the time domain.
摘要:
The invention relates to an apparatus for transfer of data elements between a bus controller, such as a CPU, and a memory controller. An address translator is arranged to receive a write address from the CPU, to modify the write address and to send the modified write address to the memory controller. An ECC calculator is arranged to receive write input data associated with the write address, from the CPU, and to generate an error correction code on the basis of the write input data. A concatenator is arranged to receive the write input data from the CPU, and to receive the error correction code from the ECC calculator, and to concatenate the write input data and the error correction code to obtain write output data, and to send the write output data to the memory controller.
摘要:
The present application relates to an apparatus for detecting software interference and the method of operating thereof. A processor and at least one shared resource form a computing shell to execute a first, functional safety critical application and at least one second application in time-shared operation. One or more performance counters are provided to adjust a counter value in response to a performance related event. A reference value storage stores one or more threshold values, each of which is associated with one of the performance counters. A comparator receives the performance counter values, compares the performance counter values with the respective threshold values and generates at least one comparison signal in response to results of the comparisons. An interference indication generator receives the at least one comparison signal and generates at least one interference indication in response to the at least one received comparison signal.
摘要:
A coding device is able to convert the data that is to be coded to data having different characteristics. The decoding device is able to decode differently coded data. The coding device utilizes measures to code the data according to various characteristics and protocols. Often the characteristics can be defined by state distributions. The decoding device can utilize information contained in the data to be decoded to characterize the data and define measures for decoding the data. Coding devices and decoding devices such as these can be used for widely differing applications.
摘要:
A method operates a system with a program-controlled unit. The program-controlled unit reads and executes data that are stored in a memory device and that represents instructions. According to the method, a check is made during the reading of data from the memory device to determine whether the relevant data are error-free. When it is ascertained that the relevant data are not error-free, the execution of an interrupt service routine is initiated. The method is distinguished by the fact that, when it is ascertained, during the execution of the interrupt service routine, that the data that are to be read from the memory device for this purpose is not error-free, the execution of the interrupt service routine is interrupted or ended, and the execution of an interrupt service routine stored at a different location is initiated. The memory device described has an error detection device that outputs an interrupt request signal if the stored data are erroneous, and that outputs a different interrupt request signal if it again discovers an error during the execution of the interrupt service routine.
摘要:
A tire pressure monitor and a method of measuring a pressure in a tire include a decision whether the tire pressure should be measured. The decision is made in dependence on a magnitude of a change in a signal which is output by a sensor which senses the pressure prevailing in the tire or the temperature prevailing in the tire. As a result it is possible to reduce the size and the weight of the components of a tire pressure monitor to be accommodated in the tire or in the rim to a minimum.
摘要:
A cache-coherent multiprocessor system comprising processing units, a shared memory resource accessible by the processing units, the shared memory resource being divided into at least one shared region, at least one first region, and at least one second region, a first cache, a second cache, a coherency unit, and a monitor unit, wherein the monitor unit is adapted to generate an error signal, when the coherency unit affects the at least one first region due to a memory access from the second processing unit and/or when the coherency unit affects the at least one second region due to a memory access from the first processing unit, and a method for detecting failures in a such a cache-coherent multiprocessor system.
摘要:
A cache-coherent multiprocessor system comprising processing units, a shared memory resource accessible by the processing units, the shared memory resource being divided into at least one shared region, at least one first region, and at least one second region, a first cache, a second cache, a coherency unit, and a monitor unit, wherein the monitor unit is adapted to generate an error signal, when the coherency unit affects the at least one first region due to a memory access from the second processing unit and/or when the coherency unit affects the at least one second region due to a memory access from the first processing unit, and a method for detecting failures in a such a cache-coherent multiprocessor system.
摘要:
A coding device for coding binary data with a particular transmit signal spectrum, the coding device having a data stream separating device for separating a data stream, which consists of the binary data to be coded, into data blocks having a predetermined data block length, a calculating device for calculating the difference between the number of binary data having a second binary state, for each data block, and a transmitting device for transmitting each data block as transformed data block or as non-transformed data block via a communication channel connected to the transmitting device, in such a manner that the total sequence of the data blocks transmitted by the transmitting device on the communication channel exhibits the particular transmit signal spectrum.