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1.发明申请CACHE-COHERENT MULTIPROCESSOR SYSTEM AND A METHOD FOR DETECTING FAILURES IN A CACHE-COHERENT MULTIPROCESSOR SYSTEM 审中-公开高速缓存多媒体处理系统和一种用于检测高速缓存多媒体系统中的故障的方法公开(公告)号：US20160034398A1
公开(公告)日：2016-02-04
申请号：US14445237
申请日：2014-07-29
IPC分类号： G06F12/08
摘要： A cache-coherent multiprocessor system comprising processing units, a shared memory resource accessible by the processing units, the shared memory resource being divided into at least one shared region, at least one first region, and at least one second region, a first cache, a second cache, a coherency unit, and a monitor unit, wherein the monitor unit is adapted to generate an error signal, when the coherency unit affects the at least one first region due to a memory access from the second processing unit and/or when the coherency unit affects the at least one second region due to a memory access from the first processing unit, and a method for detecting failures in a such a cache-coherent multiprocessor system.
摘要翻译： 一种高速缓存一致的多处理器系统，包括处理单元，由处理单元可访问的共享存储器资源，共享存储器资源被划分为至少一个共享区域，至少一个第一区域和至少一个第二区域，第一高速缓存， 第二高速缓存，一致性单元和监视器单元，其中当所述一致性单元由于来自所述第二处理单元的存储器访问而影响所述至少一个第一区域时和/或何时所述监视单元适于产生错误信号 相关性单元由于来自第一处理单元的存储器访问而影响至少一个第二区域，以及用于检测这种高速缓存相关多处理器系统中的故障的方法。
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公开(公告)号：US20160037186A1
公开(公告)日：2016-02-04
申请号：US14445718
申请日：2014-07-29
CPC分类号： H04N19/89
摘要： A method for detecting a freeze-frame condition comprises receiving a sequence of images from at least one digital device; selectively encoding a first subset of the sequence of images using a first coding scheme that causes an adjustment to an image characteristic of the selected images being encoded; selectively encoding a second subset of the sequence of images using a second coding scheme; storing the first encoded subset and second encoded subset; retrieving the stored first encoded subset and second encoded subset; selectively decoding the first subset of the selected images using the first coding scheme and selectively decoding the second subset of the selected images using the second coding scheme to re-create the sequence of images. A freeze-frame condition in the re-created sequence of images is identifiable based on a plurality of decoded images being different with respect to the image characteristic across multiple decoded image frames.
摘要翻译： 一种用于检测冻结帧状况的方法包括从至少一个数字设备接收一系列图像; 使用导致对被编码的所选择的图像的图像特征进行调整的第一编码方案来选择性地编码图像序列的第一子集; 使用第二编码方案选择性地编码图像序列的第二子集; 存储第一编码子集和第二编码子集; 检索所存储的第一编码子集和第二编码子集; 使用第一编码方案选择性地解码所选图像的第一子集，并且使用第二编码方案选择性地解码所选图像的第二子集以重新创建图像序列。 基于多个解码图像相对于跨多个解码图像帧的图像特征而不同的图像重新创建序列中的冻结帧条件是可识别的。
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3.发明申请APPARATUS AND METHOD FOR VALIDATING THE INTEGRITY OF CONTROL SIGNALS IN TIMING DOMAIN 审中-公开用于验证时域中控制信号的完整性的装置和方法公开(公告)号：US20160062331A1
公开(公告)日：2016-03-03
申请号：US14469740
申请日：2014-08-27
IPC分类号： G05B19/042
摘要： The present application relates to a signal integrity module for validating one or more control signals in time domain and a method thereof. The one or more control signals are received via a signal input from at least one control signal generating unit. A new signature is generated by a signature generating unit on the basis of a current signature and the state of the one or more control signals at a watch point. The current signature is latched into a signature register upon receiving a trigger signal. The latched signature is representative of the time course of the one or more control signals at the watch point over a monitoring period defined by the trigger signal. The latched signature is compared by a signature comparator with a pre-calculated signature to validate the integrity of the one or more control signals with respect to the time domain.
摘要翻译： 本申请涉及用于验证时域中的一个或多个控制信号的信号完整性模块及其方法。 经由至少一个控制信号产生单元输入的信号接收一个或多个控制信号。 基于当前签名和一个或多个控制信号在观察点处的状态由签名生成单元产生新的签名。 当接收到触发信号时，当前签名被锁存到签名寄存器中。 锁存的签名表示在由触发信号定义的监视时段上的观察点处的一个或多个控制信号的时间过程。 锁存的签名由签名比较器与预先计算的签名进行比较，以验证相对于时域的一个或多个控制信号的完整性。
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公开(公告)号：US20160062810A1
公开(公告)日：2016-03-03
申请号：US14469775
申请日：2014-08-27
CPC分类号： G06F11/079 , G06F11/0721 , G06F11/0757 , G06F11/0796 , G06F11/3024 , G06F11/3055 , G06F11/3409 , G06F11/348 , G06F2201/81 , G06F2201/86 , G06F2201/865 , G06F2201/88
摘要： The present application relates to an apparatus for detecting software interference and the method of operating thereof. A processor and at least one shared resource form a computing shell to execute a first, functional safety critical application and at least one second application in time-shared operation. One or more performance counters are provided to adjust a counter value in response to a performance related event. A reference value storage stores one or more threshold values, each of which is associated with one of the performance counters. A comparator receives the performance counter values, compares the performance counter values with the respective threshold values and generates at least one comparison signal in response to results of the comparisons. An interference indication generator receives the at least one comparison signal and generates at least one interference indication in response to the at least one received comparison signal.
摘要翻译： 本申请涉及一种用于检测软件干扰的装置及其操作方法。 处理器和至少一个共享资源形成计算外壳以在时间共享操作中执行第一功能安全关键应用和至少一个第二应用。 提供一个或多个性能计数器以响应于性能相关事件来调整计数器值。 参考值存储存储一个或多个阈值，每个阈值与性能计数器之一相关联。 比较器接收性能计数器值，将性能计数器值与相应的阈值进行比较，并响应于比较结果生成至少一个比较信号。 干扰指示发生器接收所述至少一个比较信号，并响应于所述至少一个接收到的比较信号而生成至少一个干扰指示。
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公开(公告)号：US20150301890A1
公开(公告)日：2015-10-22
申请号：US14258327
申请日：2014-04-22
IPC分类号： G06F11/10
CPC分类号： G06F11/1048
摘要： The invention relates to an apparatus for transfer of data elements between a bus controller, such as a CPU, and a memory controller. An address translator is arranged to receive a write address from the CPU, to modify the write address and to send the modified write address to the memory controller. An ECC calculator is arranged to receive write input data associated with the write address, from the CPU, and to generate an error correction code on the basis of the write input data. A concatenator is arranged to receive the write input data from the CPU, and to receive the error correction code from the ECC calculator, and to concatenate the write input data and the error correction code to obtain write output data, and to send the write output data to the memory controller.
摘要翻译： 本发明涉及一种用于在总线控制器（例如CPU）和存储器控制器之间传送数据元素的装置。 地址转换器被安排为从CPU接收写入地址，修改写入地址并将修改的写入地址发送到存储器控制器。 ECC计算器被布置成从CPU接收与写入地址相关联的写入输入数据，并且基于写入输入数据生成纠错码。 串联器被配置为从CPU接收写入输入数据，并从ECC计算器接收纠错码，并且连接写入输入数据和纠错码以获得写入输出数据，并发送写入输出 数据到存储器控制器。
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