公开(公告)号：US20240146416A1

公开(公告)日：2024-05-02

申请号：US17979234

申请日：2022-11-02

Applicant: Conor O'Keeffe ,  Anthony Kelly ,  Adam Herrmann ,  Finbarr O'Regan ,  Sundar Krishnamurthy ,  Amy Whitcombe ,  Ricard Menchon Enrich ,  Deepak Dasalukunte

Inventor： Conor O'Keeffe ,  Anthony Kelly ,  Adam Herrmann ,  Finbarr O'Regan ,  Sundar Krishnamurthy ,  Amy Whitcombe ,  Ricard Menchon Enrich ,  Deepak Dasalukunte

IPC: H04B10/40 ,  H04B10/112

CPC classification number: H04B10/40 ,  H04B10/112

Abstract: A method for calibrating an optical transceiver. The method can include configuring optical switches to enable routing at least one output signal of modulator circuitry operably coupled to a first receive path of a coherent optical transceiver. The method can include configuring the input to at least one modulator to generate at least one first stimulus signal. The method can include configuring a path from the first receiver analog-to-digital converter to an adaptive algorithm circuitry. The method can include adapting at least one bias setting of a photodiode associated with the first receiver in response to at least one first stimulus detected at the first receiver analog-to-digital converter to an adaptive algorithm circuitry. The method can include determining an optimum value of a photodiode associated with the first receiver.

公开(公告)号：US20240146500A1

公开(公告)日：2024-05-02

申请号：US17978582

申请日：2022-11-01

Applicant: Sundar Krishnamurthy ,  Deepak Dasalukunte ,  Conor O'Keeffe ,  Finbarr O'Regan ,  Amy Whitcombe

Inventor： Sundar Krishnamurthy ,  Deepak Dasalukunte ,  Conor O'Keeffe ,  Finbarr O'Regan ,  Amy Whitcombe

IPC: H04L7/00 ,  H04B10/079 ,  H04B10/118 ,  H04L7/033 ,  H04L7/04

CPC classification number: H04L7/0075 ,  H04B10/07955 ,  H04B10/118 ,  H04L7/0029 ,  H04L7/0331 ,  H04L7/048

Abstract: A clock data recovery (CDR) apparatus can include an interpolator circuitry to interpolate an input received signal and to generate an output signal removing the sampling clock offsets. The apparatus can include timing error detector (TED) circuitry coupled to process the output signal and to provide a timing error as feedback to the interpolator circuitry, the timing error being adjusted by gain factors used in at least one of an automatic gain control (AGC) circuitry and an orthogonalization circuitry. The apparatus can include loop filter (LF) circuitry to filter the timing error to remove noise effects. The apparatus can include numerically controlled oscillator (NCO) circuitry to adjust for a basepoint and fractional interval used to adjust resampling coefficients within the interpolator circuitry.

公开(公告)号：US20240106452A1

公开(公告)日：2024-03-28

申请号：US17955186

申请日：2022-09-28

Applicant: Amy Whitcombe ,  Brent R. Carlton ,  Sundar Krishnamurthy ,  Deepak Dasalukunte

Inventor： Amy Whitcombe ,  Brent R. Carlton ,  Sundar Krishnamurthy ,  Deepak Dasalukunte

IPC: H03M1/38 ,  H03M1/12

CPC classification number: H03M1/38 ,  H03M1/1245

Abstract: A converter can include a number of time-to-voltage converters (TVCs) each receiving an input time-domain signal. The input time-domain signal can represent a different sample than input time-domain signals of the other TVCs. The converter can also include a capacitive element coupled to outputs of the TVCs to receive a combined output signal of the TVCs. The capacitive element can provide an input capacitance of an analog-to-digital converter (ADC). Other methods and apparatuses are described.