公开(公告)号：US06977834B2

公开(公告)日：2005-12-20

申请号：US10769192

申请日：2004-01-29

申请人： Tadashi Onizawa ,  Tsuyoshi Midorikawa ,  Shigeyuki Hayakawa ,  Yutaka Tanaka

发明人： Tadashi Onizawa ,  Tsuyoshi Midorikawa ,  Shigeyuki Hayakawa ,  Yutaka Tanaka

IPC分类号： G11C11/41 ,  G11C5/06 ,  G11C11/413 ,  H01L21/8244 ,  H01L27/10 ,  H01L27/11

CPC分类号： G11C7/227 ,  G11C5/06 ,  G11C11/413

摘要： A semiconductor integrated circuit device includes normal bit cells, structural dummy bit cells and timing dummy bit cells having the same structure as that of the normal bit cells, normal word lines electrically connected to the normal bit cells, a first dummy word line electrically coupled to the structural dummy bit cells, and a second dummy word line electrically coupled to the timing dummy bit cells. The second dummy word line is connected in parallel with the first dummy word line.

摘要翻译： 半导体集成电路装置包括正常位单元，具有与正常位单元相同结构的结构虚拟位单元和定时虚拟位单元，与通常位单元电连接的通常字线，第一虚拟字线电耦合到 结构虚拟位单元，以及电耦合到定时虚拟位单元的第二虚拟字线。 第二虚拟字线与第一虚拟字线并联连接。

公开(公告)号：US20050111267A1

公开(公告)日：2005-05-26

申请号：US10769192

申请日：2004-01-29

申请人： Tadashi Onizawa ,  Tsuyoshi Midorikawa ,  Shigeyuki Hayakawa ,  Yutaka Tanaka

发明人： Tadashi Onizawa ,  Tsuyoshi Midorikawa ,  Shigeyuki Hayakawa ,  Yutaka Tanaka

IPC分类号： G11C11/41 ,  G11C5/06 ,  G11C11/413 ,  H01L21/8244 ,  H01L27/10 ,  H01L27/11

CPC分类号： G11C7/227 ,  G11C5/06 ,  G11C11/413

摘要： A semiconductor integrated circuit device includes normal bit cells, structural dummy bit cells and timing dummy bit cells having the same structure as that of the normal bit cells, normal word lines electrically connected to the normal bit cells, a first dummy word line electrically coupled to the structural dummy bit cells, and a second dummy word line electrically coupled to the timing dummy bit cells. The second dummy word line is connected in parallel with the first dummy word line.

公开(公告)号：US06563351B2

公开(公告)日：2003-05-13

申请号：US09965951

申请日：2001-09-27

申请人： Tadashi Onizawa ,  Natsuki Kushiyama ,  Masaru Koyanagi ,  Katsuki Matsudera

发明人： Tadashi Onizawa ,  Natsuki Kushiyama ,  Masaru Koyanagi ,  Katsuki Matsudera

IPC分类号： H03B100

CPC分类号： H03K19/01707 ,  H03K17/102 ,  H03K17/162

摘要： A semiconductor integrated circuit includes first and second MOS transistors and a capacitor. The first MOS transistor has a drain connected to an output terminal, a gate and a source. The second MOS transistor has a gate, a drain connected to the source of the first MOS transistor and a source and has the same conductivity type as the first MOS transistor. The capacitor has one electrode connected to the gate of the first MOS transistor and the other electrode connected to a node whose potential changes in a complementary fashion with respect to the drain potential of the first MOS transistor and functions to cancel out an influence, caused by the coupling of a mirror capacitor which exists between the gate and drain of the first MOS transistor, affecting the gate potential of the first MOS transistor.