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公开(公告)号：US06977834B2
公开(公告)日：2005-12-20
申请号：US10769192
申请日：2004-01-29
IPC分类号： G11C11/41 , G11C5/06 , G11C11/413 , H01L21/8244 , H01L27/10 , H01L27/11
CPC分类号： G11C7/227 , G11C5/06 , G11C11/413
摘要： A semiconductor integrated circuit device includes normal bit cells, structural dummy bit cells and timing dummy bit cells having the same structure as that of the normal bit cells, normal word lines electrically connected to the normal bit cells, a first dummy word line electrically coupled to the structural dummy bit cells, and a second dummy word line electrically coupled to the timing dummy bit cells. The second dummy word line is connected in parallel with the first dummy word line.
摘要翻译： 半导体集成电路装置包括正常位单元，具有与正常位单元相同结构的结构虚拟位单元和定时虚拟位单元，与通常位单元电连接的通常字线，第一虚拟字线电耦合到 结构虚拟位单元，以及电耦合到定时虚拟位单元的第二虚拟字线。 第二虚拟字线与第一虚拟字线并联连接。
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公开(公告)号：US20050111267A1
公开(公告)日：2005-05-26
申请号：US10769192
申请日：2004-01-29
IPC分类号： G11C11/41 , G11C5/06 , G11C11/413 , H01L21/8244 , H01L27/10 , H01L27/11
CPC分类号： G11C7/227 , G11C5/06 , G11C11/413
摘要： A semiconductor integrated circuit device includes normal bit cells, structural dummy bit cells and timing dummy bit cells having the same structure as that of the normal bit cells, normal word lines electrically connected to the normal bit cells, a first dummy word line electrically coupled to the structural dummy bit cells, and a second dummy word line electrically coupled to the timing dummy bit cells. The second dummy word line is connected in parallel with the first dummy word line.
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公开(公告)号：US20050280495A1
公开(公告)日：2005-12-22
申请号：US11138712
申请日：2005-05-25
CPC分类号： G11C29/027 , G11C17/18
摘要： A fuse-data reading circuit is provided in a semiconductor integrated circuit device. In the fused-data reading circuit, a differential latch circuit compares a current depending on the resistance across a first fuse element, i.e., target element, with a current depending on the resistance of a series circuit including a second fuse element used as a reference fuse element and a resistor element. The differential latch circuit determines whether the first fuse element has been cut or not.
摘要翻译： 熔丝数据读取电路设置在半导体集成电路器件中。 在熔融数据读取电路中，差分锁存电路将依赖于第一熔丝元件（即目标元件）的电阻的电流与取决于串联电路的电阻的电流进行比较，该串联电路包括用作基准的第二熔丝元件 熔丝元件和电阻元件。 差分锁存电路确定第一熔丝元件是否已被切割。
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公开(公告)号：US07495310B2
公开(公告)日：2009-02-24
申请号：US11138712
申请日：2005-05-25
IPC分类号： H01L23/62
CPC分类号： G11C29/027 , G11C17/18
摘要： A fuse-data reading circuit is provided in a semiconductor integrated circuit device. In the fused-data reading circuit, a differential latch circuit compares a current depending on the resistance across a first fuse element, i.e., target element, with a current depending on the resistance of a series circuit including a second fuse element used as a reference fuse element and a resistor element. The differential latch circuit determines whether the first fuse element has been cut or not.
摘要翻译： 熔丝数据读取电路设置在半导体集成电路器件中。 在熔融数据读取电路中，差分锁存电路将依赖于第一熔丝元件（即目标元件）的电阻的电流与取决于串联电路的电阻的电流进行比较，该串联电路包括用作基准的第二熔丝元件 熔丝元件和电阻元件。 差分锁存电路确定第一熔丝元件是否已被切割。
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5.发明授权Address converting circuit utilizing string comparison and carry information calculation 失效地址转换电路利用串比较和携带信息计算公开(公告)号：US06418520B1
公开(公告)日：2002-07-09
申请号：US09624244
申请日：2000-07-24
IPC分类号： G06F1200
CPC分类号： G06F9/342 , G06F12/1027 , G06F2212/681
摘要： Object of the present invention is to provide an address converting circuit capable of converting a virtual address that access is required into a physical address. The address converting circuit of the present invention has a CLA circuit, an adder, a CAM, a carryout selector, a physical address storing section, and a physical address selector. When adding both of the upper bit strings of the base address and the offset address that access is required, before the carryout signal from the lower bit string is calculated, addition of both of the upper bit strings in case of presuming the carryout signal as “0” and addition of both of the upper bit strings in case of presuming the carryout signal as “1” are performed. Either of the added results is selected by the carryout signal in order to perform the comparing process. Because of this, it is possible to convert into the physical address at high speed.
摘要翻译： 本发明的目的是提供一种地址转换电路，其能够将需要访问的虚拟地址转换成物理地址。本发明的地址转换电路具有CLA电路，加法器，CAM，进位选择器， 物理地址存储部分和物理地址选择器。 当在基本地址的高位列和要访问的偏移地址之间相加时，在计算来自较低位串的进位信号之前，在假设进位信号为“ 0“，并且在将进位信号设置为”1“的情况下，执行两个高位列的相加。 为了执行比较处理，通过进位信号来选择相加结果。 因此，可以高速转换成物理地址。
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6.发明授权Semiconductor memory device with delay circuit and sense amplifier circuit 失效具有延迟电路和读出放大器电路的半导体存储器件公开(公告)号：US08649231B2
公开(公告)日：2014-02-11
申请号：US13206679
申请日：2011-08-10
申请人： Tsuyoshi Midorikawa
发明人： Tsuyoshi Midorikawa
IPC分类号： G11C7/00
摘要： A memory cell is provided at an intersection of a word line and a bit line, and a dummy cell is provided at an intersection of a dummy word line and a dummy bit line. A delay circuit delays a signal read into the dummy bit line to generate a sense amplifier activating signal. A sense amplifier circuit starts an operation based on a change in the sense amplifier activating signal, and detects/amplifies a signal read out from the memory cell into the bit line. The delay circuit is configured having a first logical gate circuit and a second logical gate circuit alternately cascade-connected. A second delay time is longer than a first delay time, the second delay time being a time required for an output signal of the second logical gate circuit to switch from a first logical state to a second logical state, and a first delay time being a time required for an output signal of the first logical gate circuit to switch from a first logical state to a second logical state.
摘要翻译： 在字线和位线的交点设有存储单元，在虚拟字线和虚拟位线的交点设置虚拟单元。 延迟电路将读入虚拟位线的信号延迟以产生读出放大器激活信号。 读出放大器电路基于读出放大器激活信号的变化开始操作，并且检测/放大从存储器单元读出的信号到位线。 延迟电路被配置为具有交替级联的第一逻辑门电路和第二逻辑门电路。 第二延迟时间比第一延迟时间长，第二延迟时间是第二逻辑门电路的输出信号从第一逻辑状态切换到第二逻辑状态所需的时间，第一延迟时间为 第一逻辑门电路的输出信号从第一逻辑状态切换到第二逻辑状态所需的时间。
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公开(公告)号：US20120147683A1
公开(公告)日：2012-06-14
申请号：US13206679
申请日：2011-08-10
申请人： Tsuyoshi Midorikawa
发明人： Tsuyoshi Midorikawa
IPC分类号： G11C7/06
摘要： A memory cell is provided at an intersection of a word line and a bit line, and a dummy cell is provided at an intersection of a dummy word line and a dummy bit line. A delay circuit delays a signal read into the dummy bit line to generate a sense amplifier activating signal. A sense amplifier circuit starts an operation based on a change in the sense amplifier activating signal, and detects/amplifies a signal read out from the memory cell into the bit line. The delay circuit is configured having a first logical gate circuit and a second logical gate circuit alternately cascade-connected. A second delay time is longer than a first delay time, the second delay time being a time required for an output signal of the second logical gate circuit to switch from a first logical state to a second logical state, and a first delay time being a time required for an output signal of the first logical gate circuit to switch from a first logical state to a second logical state.
摘要翻译： 在字线和位线的交点设有存储单元，在虚拟字线和虚拟位线的交点设置虚拟单元。 延迟电路将读入虚拟位线的信号延迟以产生读出放大器激活信号。 读出放大器电路基于读出放大器激活信号的变化开始操作，并且检测/放大从存储器单元读出的信号到位线。 延迟电路被配置为具有交替级联的第一逻辑门电路和第二逻辑门电路。 第二延迟时间比第一延迟时间长，第二延迟时间是第二逻辑门电路的输出信号从第一逻辑状态切换到第二逻辑状态所需的时间，第一延迟时间为 第一逻辑门电路的输出信号从第一逻辑状态切换到第二逻辑状态所需的时间。
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