摘要:
A semiconductor integrated circuit device includes normal bit cells, structural dummy bit cells and timing dummy bit cells having the same structure as that of the normal bit cells, normal word lines electrically connected to the normal bit cells, a first dummy word line electrically coupled to the structural dummy bit cells, and a second dummy word line electrically coupled to the timing dummy bit cells. The second dummy word line is connected in parallel with the first dummy word line.
摘要:
A semiconductor integrated circuit device includes normal bit cells, structural dummy bit cells and timing dummy bit cells having the same structure as that of the normal bit cells, normal word lines electrically connected to the normal bit cells, a first dummy word line electrically coupled to the structural dummy bit cells, and a second dummy word line electrically coupled to the timing dummy bit cells. The second dummy word line is connected in parallel with the first dummy word line.
摘要:
A fuse-data reading circuit is provided in a semiconductor integrated circuit device. In the fused-data reading circuit, a differential latch circuit compares a current depending on the resistance across a first fuse element, i.e., target element, with a current depending on the resistance of a series circuit including a second fuse element used as a reference fuse element and a resistor element. The differential latch circuit determines whether the first fuse element has been cut or not.
摘要:
A fuse-data reading circuit is provided in a semiconductor integrated circuit device. In the fused-data reading circuit, a differential latch circuit compares a current depending on the resistance across a first fuse element, i.e., target element, with a current depending on the resistance of a series circuit including a second fuse element used as a reference fuse element and a resistor element. The differential latch circuit determines whether the first fuse element has been cut or not.
摘要:
Object of the present invention is to provide an address converting circuit capable of converting a virtual address that access is required into a physical address. The address converting circuit of the present invention has a CLA circuit, an adder, a CAM, a carryout selector, a physical address storing section, and a physical address selector. When adding both of the upper bit strings of the base address and the offset address that access is required, before the carryout signal from the lower bit string is calculated, addition of both of the upper bit strings in case of presuming the carryout signal as “0” and addition of both of the upper bit strings in case of presuming the carryout signal as “1” are performed. Either of the added results is selected by the carryout signal in order to perform the comparing process. Because of this, it is possible to convert into the physical address at high speed.
摘要:
A memory cell is provided at an intersection of a word line and a bit line, and a dummy cell is provided at an intersection of a dummy word line and a dummy bit line. A delay circuit delays a signal read into the dummy bit line to generate a sense amplifier activating signal. A sense amplifier circuit starts an operation based on a change in the sense amplifier activating signal, and detects/amplifies a signal read out from the memory cell into the bit line. The delay circuit is configured having a first logical gate circuit and a second logical gate circuit alternately cascade-connected. A second delay time is longer than a first delay time, the second delay time being a time required for an output signal of the second logical gate circuit to switch from a first logical state to a second logical state, and a first delay time being a time required for an output signal of the first logical gate circuit to switch from a first logical state to a second logical state.
摘要:
A memory cell is provided at an intersection of a word line and a bit line, and a dummy cell is provided at an intersection of a dummy word line and a dummy bit line. A delay circuit delays a signal read into the dummy bit line to generate a sense amplifier activating signal. A sense amplifier circuit starts an operation based on a change in the sense amplifier activating signal, and detects/amplifies a signal read out from the memory cell into the bit line. The delay circuit is configured having a first logical gate circuit and a second logical gate circuit alternately cascade-connected. A second delay time is longer than a first delay time, the second delay time being a time required for an output signal of the second logical gate circuit to switch from a first logical state to a second logical state, and a first delay time being a time required for an output signal of the first logical gate circuit to switch from a first logical state to a second logical state.