摘要:
A semiconductor integrated circuit device includes normal bit cells, structural dummy bit cells and timing dummy bit cells having the same structure as that of the normal bit cells, normal word lines electrically connected to the normal bit cells, a first dummy word line electrically coupled to the structural dummy bit cells, and a second dummy word line electrically coupled to the timing dummy bit cells. The second dummy word line is connected in parallel with the first dummy word line.
摘要:
A semiconductor integrated circuit device includes normal bit cells, structural dummy bit cells and timing dummy bit cells having the same structure as that of the normal bit cells, normal word lines electrically connected to the normal bit cells, a first dummy word line electrically coupled to the structural dummy bit cells, and a second dummy word line electrically coupled to the timing dummy bit cells. The second dummy word line is connected in parallel with the first dummy word line.
摘要:
A fuse-data reading circuit is provided in a semiconductor integrated circuit device. In the fused-data reading circuit, a differential latch circuit compares a current depending on the resistance across a first fuse element, i.e., target element, with a current depending on the resistance of a series circuit including a second fuse element used as a reference fuse element and a resistor element. The differential latch circuit determines whether the first fuse element has been cut or not.
摘要:
A fuse-data reading circuit is provided in a semiconductor integrated circuit device. In the fused-data reading circuit, a differential latch circuit compares a current depending on the resistance across a first fuse element, i.e., target element, with a current depending on the resistance of a series circuit including a second fuse element used as a reference fuse element and a resistor element. The differential latch circuit determines whether the first fuse element has been cut or not.
摘要:
There is provided a new glow plug that can be easily determined as to whether or not it is a new article.An additional circuit 12 formed by connecting a diode 13, a fuse 14, and an adjusting resistor 15 in series in this order is connected in parallel to a heating element 11 of a glow plug 1. The diode 13 is provided so as to have an anode located on the positive electrode side of the heating element 11 and a cathode located on the fuse 14 side. In the case of a unit inspection, by applying a positive voltage for test to a heating element negative electrode connecting portion 3a, it is possible to determine whether or not the glow plug 1 is normal without blowing the fuse 14 before the glow plug 1 is used in a vehicle.
摘要:
To suppress current fluctuations upon commencement of driving and prolong lifespan by reducing electric stress caused by current fluctuations.A glow plug 1, a glow switch 2, and a stabilizing coil 3 are series-connected, and upon commencement of the driving of the glow plug 1, a repetition frequency of PWM signals that control the opening and closing of the glow switch 2 is made into a higher frequency than a repetition frequency in a normal drive state and the opening and closing of the glow switch 2 is controlled (S104), and when a predetermined drive shift condition has been met (S106), the repetition frequency of the PWM signals is returned to the frequency during normal driving and the opening and closing of the glow switch 2 is controlled (S108), whereby the current upon commencement of driving is smoothed and the occurrence of an instantaneous large current is suppressed.
摘要:
A semiconductor memory device includes first and second driving transistors; first and second load transistors; and first and second transmission transistors. Their respective drain diffusion layers of the transistors are isolated from one another. The semiconductor memory device also includes a bit cell in which the first and second driving transistors, the first and second load transistors, and the first and second transmission transistors are arranged; a first wiring for connecting their respective drains of the first driving transistor, the first load transistor, and the first transmission transistor; and a second wiring for connecting their respective drains of the second driving transistor, the second load transistor, and the second transmission transistor.
摘要:
A semiconductor memory device includes first and second driving transistors; first and second load transistors; and first and second transmission transistors. Their respective drain diffusion layers of the transistors are isolated from one another. The semiconductor memory device also includes a bit cell in which the first and second driving transistors, the first and second load transistors, and the first and second transmission transistors are arranged; a first wiring for connecting their respective drains of the first driving transistor, the first load transistor, and the first transmission transistor; and a second wiring for connecting their respective drains of the second driving transistor, the second load transistor, and the second transmission transistor.
摘要:
A processing apparatus includes a sealed vacuum chamber which contains a processing portion; a pressure controlling system which keeps the internal pressure of the sealed vacuum chamber constant at a predetermined level by exhausting the ambient gas in the sealed vacuum chamber; and an ambient gas recirculating system which recirculates the ambient gas exhausted from the sealed vacuum chamber back into the sealed vacuum chamber; wherein the ambient as recirculated by the ambient gas recirculating system is blown into the sealed vacuum chamber so that a gas flow is generated in a predetermined direction along the processing portion.
摘要:
A packet recording/reproducing system is provided which records or reproduces packets on or from tracks formed in time sequence on a magnetic tape. In a recording operation, the packet recording/reproducing system adds to input packets time stamps whose values are synchronous with packet arrival time control clocks produced by the system. The timing with which the packets are recorded on the magnetic tape is controlled by the arrival time control clocks so that a given number of the packets inputted at high data rate are recorded within a one-track area, a two-track area, or a one-track over area defined across at least two of the tracks, thereby minimizing the loss of capacity of the magnetic tape.