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1.发明授权公开(公告)号：US07829428B1
公开(公告)日：2010-11-09
申请号：US12229689
申请日：2008-08-26
申请人： Yaojian Leng , Rodney Hill , Terry Lines
发明人： Yaojian Leng , Rodney Hill , Terry Lines
IPC分类号： H01L21/20
CPC分类号： H01L28/20
摘要： A method is disclosed for eliminating a mask layer during the manufacture of thin film resistor circuits. The method of the present invention enables the simultaneous etching of both deep vias and shallow vias using one mask layer instead of two mask layers. A high selectivity film layer of silicon nitride is formed on the ends of a thin film resistor layer. The thickness of the silicon nitride causes the etch time for a shallow via to the thin film resistor to be approximately equal to an etch time for a deep via that is etched through dielectric material to an underlying patterned metal layer.
摘要翻译： 公开了在制造薄膜电阻器电路期间消除掩模层的方法。 本发明的方法能够使用一个掩模层而不是两个掩模层同时蚀刻深通孔和浅通孔。 在薄膜电阻层的端部上形成氮化硅的高选择性膜层。 氮化硅的厚度导致薄通孔到薄膜电阻器的蚀刻时间近似等于通过电介质材料蚀刻到下面的图案化金属层的深通孔的蚀刻时间。
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2.发明授权Depletion-mode transistor that eliminates the need to separately set the threshold voltage of the depletion-mode transistor 有权消耗型晶体管消除了分别设置耗尽型晶体管的阈值电压的需要公开(公告)号：US07161216B1
公开(公告)日：2007-01-09
申请号：US10692255
申请日：2003-10-22
申请人： Terry Lines
发明人： Terry Lines
IPC分类号： H01L29/76
CPC分类号： H01L27/11526 , H01L21/823842 , H01L21/82385 , H01L27/0883 , H01L27/0922 , H01L27/105 , H01L27/11546 , H01L29/42324
摘要： A semiconductor circuit with a depletion-mode transistor is formed with a method that eliminates the need for a separate mask and implant step to set the threshold voltage of the depletion-mode transistor. As a result, the method of the present invention reduces the cost and complexity associated with the fabrication of a semiconductor circuit that includes a depletion-mode transistor.
摘要翻译： 具有耗尽型晶体管的半导体电路通过不需要单独的掩模和注入步骤来设置耗尽型晶体管的阈值电压的方法来形成。 结果，本发明的方法降低了与包括耗尽型晶体管的半导体电路的制造相关的成本和复杂性。
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3.发明授权System and method for selectively modifying a wet etch rate in a large area 有权用于在大面积上选择性地改变湿蚀刻速率的系统和方法公开(公告)号：US07172973B1
公开(公告)日：2007-02-06
申请号：US10979622
申请日：2004-11-02
IPC分类号： H01L21/302
CPC分类号： H01L21/30604 , H01L21/3083
摘要： A system and method is disclosed for selectively increasing a wet etch rate of a large raised area portion of a semiconductor wafer with respect to a wet etch rate of a small raised area portion of the semiconductor wafer. A resist mask on the semiconductor wafer is etched to create a large via over the large raised area portion and a small via over the small raised area portion. An ion implantation beam is applied with an impact direction that enables ions to pass through the large via but does not enable ions to pass through the small via. The ions that pass through the large via increase the wet etch rate of the underlying portion of the semiconductor wafer. In one embodiment the impact direction has a tilt angle of forty five degrees and a rotation angle of forty five degrees.
摘要翻译： 公开了一种用于相对于半导体晶片的小凸起区域部分的湿蚀刻速率选择性地增加半导体晶片的大凸起部分的湿蚀刻速率的系统和方法。 蚀刻半导体晶片上的抗蚀剂掩模以在大的凸起部分上形成大的通孔，并在小的凸起部分上形成小的通孔。 施加离子注入束的冲击方向使得离子能够通过大通孔，但不能使离子通过小通孔。 通过大通孔的离子增加了半导体晶片的下面部分的湿蚀刻速率。 在一个实施例中，冲击方向具有四十五度的倾斜角和四十五度的旋转角。
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4.发明授权Method for forming a depletion-mode transistor that eliminates the need to separately set the threshold voltage of the depletion-mode transistor 有权用于形成耗尽型晶体管的方法，其消除了分别设置耗尽型晶体管的阈值电压的需要公开(公告)号：US07144795B1
公开(公告)日：2006-12-05
申请号：US10729491
申请日：2003-12-04
申请人： Terry Lines
发明人： Terry Lines
IPC分类号： H01L21/425 , H01L21/22 , H01L21/38 , H01L21/336
CPC分类号： H01L27/11526 , H01L21/823842 , H01L21/82385 , H01L27/0883 , H01L27/0922 , H01L27/105 , H01L27/11546 , H01L29/42324
摘要： A semiconductor circuit with a depletion-mode transistor is formed with a method that eliminates the need for a separate mask and implant step to set the threshold voltage of the depletion-mode transistor. As a result, the method of the present invention reduces the cost and complexity associated with the fabrication of a semiconductor circuit that includes a depletion-mode transistor.
摘要翻译： 具有耗尽型晶体管的半导体电路通过不需要单独的掩模和注入步骤来设置耗尽型晶体管的阈值电压的方法来形成。 结果，本发明的方法降低了与包括耗尽型晶体管的半导体电路的制造相关的成本和复杂性。
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5.发明授权Depletion-mode transistor that eliminates the need to separately set the threshold voltage of the depletion-mode transistor 有权消耗型晶体管消除了分别设置耗尽型晶体管的阈值电压的需要公开(公告)号：US06703670B1
公开(公告)日：2004-03-09
申请号：US09824653
申请日：2001-04-03
申请人： Terry Lines
发明人： Terry Lines
IPC分类号： H01L2976
CPC分类号： H01L27/11526 , H01L21/823842 , H01L21/82385 , H01L27/0883 , H01L27/0922 , H01L27/105 , H01L27/11546 , H01L29/42324
摘要： A semiconductor circuit with a depletion-mode transistor is formed with a method that eliminates the need for a separate mask and implant step to set the threshold voltage of the depletion-mode transistor. As a result, the method of the present invention reduces the cost and complexity associated with the fabrication of a semiconductor circuit that includes a depletion-mode transistor.
摘要翻译： 具有耗尽型晶体管的半导体电路通过不需要单独的掩模和注入步骤来设置耗尽型晶体管的阈值电压的方法来形成。 结果，本发明的方法降低了与包括耗尽型晶体管的半导体电路的制造相关的成本和复杂性。
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