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公开(公告)号：US20120126291A1
公开(公告)日：2012-05-24
申请号：US13278798
申请日：2011-10-21
IPC分类号： H01L27/092
CPC分类号： H01L27/085 , H01L27/0605 , H01L29/66462 , H01L29/7785 , H01L29/802
摘要： A semiconductor device including at least a p-channel field-effect transistor region formed above a compound semiconductor substrate. The p-channel field-effect transistor region includes an undoped buffer layer; a p-type channel layer formed in contact with the buffer layer; a p-type source region and a p-type drain region formed in the channel layer, being separated with each other; and an n-type gate region formed above the channel layer and between the source region and the drain region. The buffer layer is formed having either a multilayer structure including a hole diffusion control layer with a band gap larger than the channel layer, or a single layer structure including only the hole diffusion control layer.
摘要翻译： 一种半导体器件，包括至少形成在化合物半导体衬底上的p沟道场效应晶体管区域。 p沟道场效应晶体管区域包括未掺杂的缓冲层; 形成为与缓冲层接触的p型沟道层; 形成在沟道层中的p型源极区和p型漏极区彼此分离; 以及形成在沟道层上方且在源极区域和漏极区域之间的n型栅极区域。 缓冲层形成为具有包括带隙大于沟道层的空穴扩散控制层的多层结构，或仅包括孔扩散控制层的单层结构。
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公开(公告)号：US08698202B2
公开(公告)日：2014-04-15
申请号：US13278798
申请日：2011-10-21
IPC分类号： H01L29/66
CPC分类号： H01L27/085 , H01L27/0605 , H01L29/66462 , H01L29/7785 , H01L29/802
摘要： A semiconductor device including at least a p-channel field-effect transistor region formed above a compound semiconductor substrate. The p-channel field-effect transistor region includes an undoped buffer layer; a p-type channel layer formed in contact with the buffer layer; a p-type source region and a p-type drain region formed in the channel layer, being separated with each other; and an n-type gate region formed above the channel layer and between the source region and the drain region. The buffer layer is formed having either a multilayer structure including a hole diffusion control layer with a band gap larger than the channel layer, or a single layer structure including only the hole diffusion control layer.
摘要翻译： 一种半导体器件，包括至少形成在化合物半导体衬底上的p沟道场效应晶体管区域。 p沟道场效应晶体管区域包括未掺杂的缓冲层; 形成为与缓冲层接触的p型沟道层; 形成在沟道层中的p型源极区和p型漏极区彼此分离; 以及形成在沟道层上方且在源极区域和漏极区域之间的n型栅极区域。 缓冲层形成为具有包括带隙大于沟道层的空穴扩散控制层的多层结构，或仅包括孔扩散控制层的单层结构。
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公开(公告)号：US08575658B2
公开(公告)日：2013-11-05
申请号：US13538583
申请日：2012-06-29
IPC分类号： H01L29/80
CPC分类号： H01L29/7787 , H01L21/8252 , H01L27/0605 , H01L27/098 , H01L29/205 , H01L29/66462
摘要： A semiconductor device includes a compound semiconductor substrate; a first conductivity type-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a first channel layer; a first conductivity type first barrier layer that forms a heterojunction with the first channel layer, and supplies a first conductivity type charge to the first channel layer; and a second conductivity type gate region that has a pn junction-type potential barrier against the first conductivity type first barrier layer; and a second conductivity type-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a second conductivity type second channel layer, and a first conductivity type gate region that has a pn junction-type potential barrier against the second conductivity type second channel layer.
摘要翻译： 半导体器件包括化合物半导体衬底; 形成在所述化合物半导体衬底上的第一导电型沟道场效应晶体管区，并且包括第一沟道层; 第一导电型第一阻挡层，与第一沟道层形成异质结，并向第一沟道层提供第一导电型电荷; 以及对所述第一导电型第一阻挡层具有pn结型势垒的第二导电型栅极区; 以及形成在所述化合物半导体衬底上并且包括第二导电类型的第二沟道层的第二导电类型沟道场效应晶体管区域和具有抵抗第二导电性的pn结型势垒的第一导电型栅极区 键入第二通道层。
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公开(公告)号：US20120056273A1
公开(公告)日：2012-03-08
申请号：US13219007
申请日：2011-08-26
申请人： Yuji Ishii , Yuji Ibusuki , Hideki Tanaka , Kentaro Kasai
发明人： Yuji Ishii , Yuji Ibusuki , Hideki Tanaka , Kentaro Kasai
IPC分类号： H01L27/088 , H01L21/8232
CPC分类号： H01L27/0705 , H01L21/84 , H01L27/1207 , H01L29/78
摘要： A semiconductor device includes: a first transistor formed on a semiconductor substrate; and a second transistor formed above the semiconductor substrate with an insulation film interposed therebetween. The first transistor includes a first body region formed on a surface of the semiconductor substrate, and a first source region and a first drain region formed so as to sandwich the first body region, the second transistor includes a semiconductor layer formed on the insulation film, a second body region formed in a part of the semiconductor layer, a second source region and a second drain region formed so as to sandwich the second body region in the semiconductor layer, agate insulation film formed on the body region of the semiconductor layer, and agate electrode formed on the gate insulation film, and the second drain region is disposed on the first body region.
摘要翻译： 半导体器件包括：形成在半导体衬底上的第一晶体管; 以及形成在半导体衬底上方的绝缘膜之间的第二晶体管。 第一晶体管包括形成在半导体衬底的表面上的第一体区和形成为夹住第一体区的第一源区和第一漏区，第二晶体管包括形成在绝缘膜上的半导体层， 形成在半导体层的一部分中的第二体区，形成为将半导体层中的第二体区夹持的第二源极区和第二漏极区，形成在半导体层的体区的玛瑙绝缘膜，以及 形成在栅极绝缘膜上的玛瑙电极，并且第二漏极区域设置在第一体区域上。
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公开(公告)号：US08378389B2
公开(公告)日：2013-02-19
申请号：US12805160
申请日：2010-07-15
IPC分类号： H01L29/80
CPC分类号： H01L29/7787 , H01L21/8252 , H01L27/0605 , H01L27/098 , H01L29/205 , H01L29/66462
摘要： A semiconductor device includes: a compound semiconductor substrate; an n-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a first channel layer; an n-type first barrier layer that forms a heterojunction with the first channel layer, and supplies an n-type charge to the first channel layer; and a p-type gate region that has a pn junction-type potential barrier against the n-type first barrier layer; and a p-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a p-type second channel layer, and an n-type gate region that has a pn junction-type potential barrier against the p-type second channel layer.
摘要翻译： 半导体器件包括：化合物半导体衬底; 形成在所述化合物半导体衬底上并且包括第一沟道层的n沟道场效应晶体管区; n型第一阻挡层，与第一沟道层形成异质结，并向第一沟道层提供n型电荷; 以及对n型第一阻挡层具有pn结型势垒的p型栅极区域; 以及形成在化合物半导体衬底上的p沟道场效应晶体管区，并且包括p型第二沟道层和对p型第二沟道pn结型势垒的n型栅极区 通道层。
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公开(公告)号：US20120267684A1
公开(公告)日：2012-10-25
申请号：US13538583
申请日：2012-06-29
IPC分类号： H01L27/085 , H01L21/8232
CPC分类号： H01L29/7787 , H01L21/8252 , H01L27/0605 , H01L27/098 , H01L29/205 , H01L29/66462
摘要： A semiconductor device includes a compound semiconductor substrate; a first conductivity type-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a first channel layer; a first conductivity type first barrier layer that forms a heterojunction with the first channel layer, and supplies a first conductivity type charge to the first channel layer; and a second conductivity type gate region that has a pn junction-type potential barrier against the first conductivity type first barrier layer; and a second conductivity type-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a second conductivity type second channel layer, and a first conductivity type gate region that has a pn junction-type potential barrier against the second conductivity type second channel layer.
摘要翻译： 半导体器件包括化合物半导体衬底; 形成在所述化合物半导体衬底上的第一导电型沟道场效应晶体管区，并且包括第一沟道层; 第一导电型第一阻挡层，与第一沟道层形成异质结，并向第一沟道层提供第一导电型电荷; 以及对所述第一导电型第一阻挡层具有pn结型势垒的第二导电型栅极区; 以及形成在所述化合物半导体衬底上并且包括第二导电类型的第二沟道层的第二导电类型沟道场效应晶体管区域和具有针对所述第二导电性的pn结型势垒的第一导电型栅极区 键入第二通道层。
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公开(公告)号：US20110024798A1
公开(公告)日：2011-02-03
申请号：US12805160
申请日：2010-07-15
IPC分类号： H01L27/085 , H01L21/8238 , H01L21/335 , H01L29/778
CPC分类号： H01L29/7787 , H01L21/8252 , H01L27/0605 , H01L27/098 , H01L29/205 , H01L29/66462
摘要： A semiconductor device includes: a compound semiconductor substrate; an n-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a first channel layer; an n-type first barrier layer that forms a heterojunction with the first channel layer, and supplies an n-type charge to the first channel layer; and a p-type gate region that has a pn junction-type potential barrier against the n-type first barrier layer; and a p-channel field-effect transistor region formed on the compound semiconductor substrate, and that includes a p-type second channel layer, and an n-type gate region that has a pn junction-type potential barrier against the p-type second channel layer.
摘要翻译： 半导体器件包括：化合物半导体衬底; 形成在所述化合物半导体衬底上并且包括第一沟道层的n沟道场效应晶体管区; n型第一阻挡层，与第一沟道层形成异质结，并向第一沟道层提供n型电荷; 以及对n型第一阻挡层具有pn结型势垒的p型栅极区域; 以及形成在化合物半导体衬底上的p沟道场效应晶体管区，并且包括p型第二沟道层和对p型第二沟道pn结型势垒的n型栅极区 通道层。
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