公开(公告)号：US20190221560A1

公开(公告)日：2019-07-18

申请号：US16329348

申请日：2017-08-21

申请人： CSMC TECHNOLOGIES FAB2 CO., LTD.

发明人： Yan GU ,  Shikang CHENG ,  Sen ZHANG

IPC分类号： H01L27/07 ,  H01L21/8234

CPC分类号： H01L27/0705 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823487 ,  H01L21/823493 ,  H01L27/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/808

摘要： A device integrated with a depletion-mode junction field-effect transistor and a method for manufacturing the device. The device includes: a well region, which is of a second conduction type and formed within a first conduction region (214); a JFET source (210), which is of a first conduction type and formed within the well region; a metal electrode (212) of the JFET sources formed on the JFET sources (210), which is in contact with the JFET sources (210); a lateral channel region (208), which is of the first conduction type and formed between two adjacent JFET sources (210), while two ends thereof are in contact with the two adjacent JFET sources (210); and a JFET metal gate (213) formed on the well region.

公开(公告)号：US20190189556A1

公开(公告)日：2019-06-20

申请号：US15848026

申请日：2017-12-20

申请人： NATIONAL CHUNG SHAN INSTITUTE OF SCIENCE AND TECHNOLOGY

发明人： CHIA-JEN LIANG ,  YEN-CHENG KUAN ,  CHING-WEN CHIANG ,  CHIEN-TE YU

IPC分类号： H01L23/522 ,  H01F21/12 ,  H01L27/07

CPC分类号： H01L23/5227 ,  H01F21/12 ,  H01L27/0705

摘要： A variable inductor which comprises a primary conductor, first and second secondary conductors and one or more switch. The primary conductor has a first node and a second node, wherein the first node is used to connect a first external component and the second node is used to connect a second external component. The first and second secondary conductors magnetically couple to the primary conductor. The one or more switch has two sides connected to the first or second secondary conductor, respectively. The first and second secondary conductors are formed a single-loop structure with two or more changeable current paths which are operated by the states of the one or more switch. An integrated circuit using the variable inductor is also introduced.

公开(公告)号：US20180374840A1

公开(公告)日：2018-12-27

申请号：US16061900

申请日：2016-12-22

申请人： SONY CORPORATION

发明人： Katsuhiko FUKASAKU ,  Daisuke NAKAGAWA

IPC分类号： H01L27/02 ,  H01L27/07 ,  H01L23/60

CPC分类号： H01L27/0274 ,  H01L21/822 ,  H01L23/60 ,  H01L27/0277 ,  H01L27/0285 ,  H01L27/04 ,  H01L27/0629 ,  H01L27/0705 ,  H03K19/00361

摘要： The present technology relates to a semiconductor integrated circuit which operates with a low voltage and is capable of preventing destruction of a protection circuit and a control method thereof. The semiconductor integrated circuit includes a resistance element and a capacitance element connected between a power supply line and a ground line in series, an inverter of which an input is connected between the resistance element and the capacitance element, a MOS transistor of which a gate electrode is connected to an output of the inverter and a drain electrode and a source electrode are respectively connected to the power supply line and the ground line, and a current limit element inserted between a well region where the MOS transistor is formed and the gate electrode. The present technology is applied to, for example, the protection circuit for preventing destruction of an internal circuit by ESD and the like.

公开(公告)号：US20180358356A1

公开(公告)日：2018-12-13

申请号：US15619811

申请日：2017-06-12

申请人： Micron Technology, Inc.

发明人： Toshinao Ishii ,  Yasuhiko Tanuma

IPC分类号： H01L27/06 ,  H01L23/525

CPC分类号： H01L27/0617 ,  H01L23/5252 ,  H01L27/0705

摘要： An apparatus comprises an antifuse cell comprising first and second nodes, an antifuse element, and a transistor. The antifuse element and the transistor are coupled in series between the first and second nodes. The antifuse element comprises an antifuse gate. The transistor comprises a transistor gate comprising a substantially-annular structure substantially surrounding the antifuse gate.

公开(公告)号：US10014048B2

公开(公告)日：2018-07-03

申请号：US15486051

申请日：2017-04-12

申请人： SK hynix Inc.

发明人： Dong Uc Ko

IPC分类号： G11C11/00 ,  G11C11/412 ,  H01L27/11 ,  H01L27/07 ,  H01L27/02 ,  G11C11/417 ,  H01L23/528

CPC分类号： G11C11/412 ,  G11C7/106 ,  G11C7/1087 ,  G11C11/417 ,  H01L23/528 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/0705 ,  H01L27/1104 ,  H03K3/037 ,  H03K3/356113

摘要： A dual interlocked storage cell (DICE) latch may be provided. A semiconductor device may be provided. The semiconductor device may include a DICE latch.

公开(公告)号：US20180175024A1

公开(公告)日：2018-06-21

申请号：US15686795

申请日：2017-08-25

申请人： Samsung Electronics Co., Ltd.

发明人： Jung-ho DO ,  Sang-hoon Baek ,  Tae-joong Song ,  Jong-hoon Jung ,  Seung-young Lee

IPC分类号： H01L27/088 ,  H01L23/528 ,  H01L29/78 ,  H01L27/07 ,  H01L27/02 ,  H01L29/417 ,  H01L23/522

CPC分类号： H01L27/088 ,  H01L21/823487 ,  H01L21/823885 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0705 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/41741 ,  H01L29/7827

摘要： An integrated circuit having a vertical transistor includes first through fourth gate lines extending in a first direction and sequentially arranged in parallel with each other, a first top active region over the first through third gate lines and insulated from the second gate line, and a second top active region. The first top active region forms first and third transistors with the first and third gate lines respectively. The second top active region is over the second through fourth gate lines and insulated from the third gate line. The second top active region forms second and fourth transistors with the second and fourth gate lines respectively.

公开(公告)号：US09997463B2

公开(公告)日：2018-06-12

申请号：US15191359

申请日：2016-06-23

申请人： STMicroelectronics, Inc.

发明人： John H. Zhang

IPC分类号： H01L27/115 ,  H01L29/06 ,  H01L29/423 ,  H01L27/06 ,  H01L29/08 ,  H01L27/07 ,  H01L27/02 ,  H01L29/786 ,  H01L29/66 ,  H01L29/788 ,  H01L23/538 ,  H01L29/417 ,  H01L29/775 ,  H01L29/792 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/11582 ,  H01L29/51

CPC分类号： H01L23/5386 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823871 ,  H01L21/823885 ,  H01L23/5384 ,  H01L27/0255 ,  H01L27/0688 ,  H01L27/0705 ,  H01L27/0727 ,  H01L27/092 ,  H01L27/11582 ,  H01L29/0676 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78696 ,  H01L29/7926

摘要： A modular interconnect structure facilitates building complex, yet compact, integrated circuits from vertical GAA FETs. The modular interconnect structure includes annular metal contacts to the transistor terminals, sectors of stacked discs extending radially outward from the vertical nanowires, and vias in the form of rods. Extension tabs mounted onto the radial sector interconnects permit signals to fan out from each transistor terminal. Adjacent interconnects are linked by linear segments. Unlike conventional integrated circuits, the modular interconnects as described herein are formed at the same time as the transistors. Vertical GAA NAND and NOR gates provide building blocks for creating all types of logic gates to carry out any desired Boolean logic function. Stacked vertical GAA FETs are made possible by the modular interconnect structure. The modular interconnect structure permits a variety of specialized vertical GAA devices to be integrated on a silicon substrate using standard CMOS processes.

公开(公告)号：US20180130518A1

公开(公告)日：2018-05-10

申请号：US15486051

申请日：2017-04-12

申请人： SK hynix Inc.

发明人： Dong Uc KO

IPC分类号： G11C11/412 ,  H01L27/11 ,  H01L27/07 ,  H01L27/02 ,  G11C11/417 ,  H01L23/528

CPC分类号： G11C11/412 ,  G11C7/106 ,  G11C7/1087 ,  G11C11/417 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0705 ,  H01L27/1104 ,  H03K3/037 ,  H03K3/356113

摘要： A dual interlocked storage cell (DICE) latch may be provided. A semiconductor device may be provided. The semiconductor device may include a DICE latch.

公开(公告)号：US09964987B2

公开(公告)日：2018-05-08

申请号：US15161585

申请日：2016-05-23

申请人： Taiwan Semiconductor Manufacturing CO., LTD.

发明人： Ching-Ho Chang ,  Jaw-Juinn Horng ,  Yung-Chow Peng

IPC分类号： H01L27/118 ,  H01L21/82 ,  G05F3/26 ,  H01L29/423 ,  H01L27/06 ,  H01L27/07 ,  H01L27/10 ,  G06F17/50

CPC分类号： G05F3/262 ,  G06F17/5072 ,  H01L27/0617 ,  H01L27/0705 ,  H01L27/10 ,  H01L29/42376

摘要： A current mirror circuit includes a first current mirror leg and a second current mirror leg. The first current mirror leg is configured with N stages of first transistors coupled in series and with their respective gates tied together. The second current mirror leg is configured with N stages of second transistors coupled in series and with their respective gates tied together. The first transistors and the second transistors are implemented within a transistor array, the first transistors and the second transistors are coupled between a first reference terminal and a second reference terminal, the first transistors and the second transistors at 1st to Kth stages adjacent to the first reference terminal are implemented at corner regions of the transistor array, N and K are positive integers and K

公开(公告)号：US09941155B2

公开(公告)日：2018-04-10

申请号：US15596288

申请日：2017-05-16

申请人： Micron Technology, Inc.

发明人： Luan C. Tran

IPC分类号： H01L27/115 ,  H01L27/07 ,  H01L21/768 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11546 ,  H01L23/522 ,  H01L27/1157

CPC分类号： H01L21/76816 ,  H01L21/02518 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28273 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0705 ,  H01L27/11517 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11546 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/66477 ,  H01L29/66825 ,  H01L29/788

摘要： Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains. The select gates are biased in the off state to prevent current flow from the mid-portion of the loop's legs to the blocks, thereby electrically isolating the mid-portions from the ends of the loops and also electrically isolating different legs of a loop from each other.