公开(公告)号：US20220415723A1

公开(公告)日：2022-12-29

申请号：US17360834

申请日：2021-06-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： RAHUL AGARWAL ,  DEAN GONZALES

IPC: H01L21/66 ,  H01L23/498 ,  H01L21/48

Abstract: A chip for wafer-level testing of fanout chiplet, including: a die; a carrier substrate; a plurality of redistribution layers applied to the carrier substrate; and one or more first conductive pathways in the plurality of redistribution layers, wherein the one or more first conductive pathways each comprise a first end coupled to a corresponding input/output connection point of the die and a second end coupled to a corresponding probing site, wherein the one or more first conductive pathways are not routed through the carrier substrate.

公开(公告)号：US20230195678A1

公开(公告)日：2023-06-22

申请号：US17692147

申请日：2022-03-10

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： PRADEEP JAYARAMAN ,  DEAN GONZALES ,  GERALD R. TALBOT ,  RAMON A. MANGASER ,  MICHAEL J. TRESIDDER ,  PRASANT KUMAR VALLUR ,  SRIKANTH REDDY GRUDDANTI ,  KRISHNA REDDY MUDIMELA VENKATA ,  DAVID H. MCINTYRE

IPC: G06F13/42

CPC classification number: G06F13/4291 ,  G06F13/4286 ,  H01L25/0652

Abstract: A semiconductor package for skew matching in a die-to-die interface, including: a first die; a second die aligned with the first die such that each connection point of a first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die; and a plurality of connection paths of a substantially same length, wherein each connection path of the plurality of connection paths couples a respective connection point of the first plurality of connection points to the corresponding connection point of the second plurality of connection points.