公开(公告)号：US12086447B2

公开(公告)日：2024-09-10

申请号：US16719076

申请日：2019-12-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Khaled Hamidouche ,  Michael W. Lebeane ,  Hari S. Thangirala

IPC: G06F3/06 ,  G06F12/0882

CPC classification number: G06F3/0647 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0688 ,  G06F12/0882 ,  G06F2212/7201

Abstract: A processing system includes a first processor couplable to a first memory and a second memory. In response to a page migration trigger for a page in the first memory, the first processor is configured to, responsive to the page being a read-only page storing code for execution, initiate migration of the page to a code cache portion of a second memory associated with a second processor and shared by multiple processes executing at the second processor, and to configure each process of a set of processes executing at the second processor to access and execute the code from the code cache portion.

公开(公告)号：US10684957B2

公开(公告)日：2020-06-16

申请号：US16110062

申请日：2018-08-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael W. Lebeane ,  Seunghee Shin

IPC: G06F12/00 ,  G06F12/10

Abstract: An apparatus and method performs neighborhood-aware virtual to physical address translations. A coalescing opportunity for a first virtual address is determined, based on completing a memory access corresponding to a page walk for a second virtual address. Metadata corresponding to the first virtual address is provided to a page table walk buffer based on the coalescing opportunity and a page walk for the first virtual address is performed based on the metadata corresponding to the first virtual address.