公开(公告)号：US20220318012A1

公开(公告)日：2022-10-06

申请号：US17217792

申请日：2021-03-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Muhammad Amber HASSAAN ,  Michael L. CHU ,  Ashwin AJI

IPC: G06F9/30

Abstract: A processing system includes a processing unit and a memory device. The memory device includes a processing-in-memory (PIM) module that performs processing operations on behalf of the processing unit. An instruction set architecture (ISA) of the PIM module has fewer instructions than an ISA of the processing unit. Instructions received from the processing unit are translated such that processing resources of the PIM module are virtualized. As a result, the PIM module concurrently performs processing operations for multiple threads or applications of the processing unit.

公开(公告)号：US20200098082A1

公开(公告)日：2020-03-26

申请号：US16138708

申请日：2018-09-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Anthony GUTIERREZ ,  Muhammad Amber HASSAAN ,  Sooraj PUTHOOR

IPC: G06T1/60 ,  G06T1/20 ,  G06F12/02 ,  G06F9/30

Abstract: A processing unit includes one or more processor cores and a set of registers to store configuration information for the processing unit. The processing unit also includes a coprocessor configured to receive a request to modify a memory allocation for a kernel concurrently with the kernel executing on the at least one processor core. The coprocessor is configured to modify the memory allocation by modifying the configuration information stored in the set of registers. In some cases, initial configuration information is provided to the set of registers by a different processing unit. The initial configuration information is stored in the set of registers prior to the coprocessor modifying the configuration information.

公开(公告)号：US20230229494A1

公开(公告)日：2023-07-20

申请号：US18095704

申请日：2023-01-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Muhammad Amber HASSAAN ,  Anirudh Mohan KAUSHIK ,  Sooraj PUTHOOR ,  Gokul Subramanian RAVI ,  Bradford BECKMANN ,  Ashwin AJI

IPC: G06F9/48 ,  G06F9/52 ,  G06F16/901

CPC classification number: G06F9/4881 ,  G06F9/52 ,  G06F16/9024 ,  G06F2209/486

Abstract: A processor includes a task scheduling unit and a compute unit coupled to the task scheduling unit. The task scheduling unit performs a task dependency assessment of a task dependency graph and task data requirements that correspond to each task of the plurality of tasks. Based on the task dependency assessment, the task scheduling unit schedules a first task of the plurality of tasks and a second proxy object of a plurality of proxy objects specified by the task data requirements such that a memory transfer of the second proxy object of the plurality of proxy objects occurs while the first task is being executed.

公开(公告)号：US20210294646A1

公开(公告)日：2021-09-23

申请号：US16824601

申请日：2020-03-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Muhammad Amber HASSAAN ,  Anirudh Mohan KAUSHIK ,  Sooraj PUTHOOR ,  Gokul Subramanian RAVI ,  Bradford BECKMANN ,  Ashwin AJI

IPC: G06F9/48 ,  G06F16/901 ,  G06F9/52

Abstract: A processor includes a task scheduling unit and a compute unit coupled to the task scheduling unit. The task scheduling unit performs a task dependency assessment of a task dependency graph and task data requirements that correspond to each task of the plurality of tasks. Based on the task dependency assessment, the task scheduling unit schedules a first task of the plurality of tasks and a second proxy object of a plurality of proxy objects specified by the task data requirements such that a memory transfer of the second proxy object of the plurality of proxy objects occurs while the first task is being executed.