公开(公告)号：US20220318012A1

公开(公告)日：2022-10-06

申请号：US17217792

申请日：2021-03-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Muhammad Amber HASSAAN ,  Michael L. CHU ,  Ashwin AJI

IPC: G06F9/30

Abstract: A processing system includes a processing unit and a memory device. The memory device includes a processing-in-memory (PIM) module that performs processing operations on behalf of the processing unit. An instruction set architecture (ISA) of the PIM module has fewer instructions than an ISA of the processing unit. Instructions received from the processing unit are translated such that processing resources of the PIM module are virtualized. As a result, the PIM module concurrently performs processing operations for multiple threads or applications of the processing unit.

公开(公告)号：US20220092724A1

公开(公告)日：2022-03-24

申请号：US17030024

申请日：2020-09-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Niti MADAN ,  Michael L. CHU ,  Ashwin AJI

IPC: G06T1/60 ,  G06F9/50 ,  G06F3/06 ,  G06T1/20

Abstract: One or more processing units, such as a graphics processing unit (GPU), execute an application. A resource manager selectively allocates a first memory portion or a second memory portion to the processing units based on memory access characteristics. The first memory portion has a first latency that is lower that a second latency of the second memory portion. In some cases, the memory access characteristics indicate a latency sensitivity. In some cases, hints included in corresponding program code are used to determine the memory access characteristics. The memory access characteristics can also be determined by monitoring memory access requests, measuring a cache miss rate or a row buffer miss rate for the monitored memory access requests, and determining the memory access characteristics based on the cache miss rate or the row buffer miss rate.

公开(公告)号：US20230229494A1

公开(公告)日：2023-07-20

申请号：US18095704

申请日：2023-01-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Muhammad Amber HASSAAN ,  Anirudh Mohan KAUSHIK ,  Sooraj PUTHOOR ,  Gokul Subramanian RAVI ,  Bradford BECKMANN ,  Ashwin AJI

IPC: G06F9/48 ,  G06F9/52 ,  G06F16/901

CPC classification number: G06F9/4881 ,  G06F9/52 ,  G06F16/9024 ,  G06F2209/486

Abstract: A processor includes a task scheduling unit and a compute unit coupled to the task scheduling unit. The task scheduling unit performs a task dependency assessment of a task dependency graph and task data requirements that correspond to each task of the plurality of tasks. Based on the task dependency assessment, the task scheduling unit schedules a first task of the plurality of tasks and a second proxy object of a plurality of proxy objects specified by the task data requirements such that a memory transfer of the second proxy object of the plurality of proxy objects occurs while the first task is being executed.

公开(公告)号：US20210294646A1

公开(公告)日：2021-09-23

申请号：US16824601

申请日：2020-03-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Muhammad Amber HASSAAN ,  Anirudh Mohan KAUSHIK ,  Sooraj PUTHOOR ,  Gokul Subramanian RAVI ,  Bradford BECKMANN ,  Ashwin AJI

IPC: G06F9/48 ,  G06F16/901 ,  G06F9/52

Abstract: A processor includes a task scheduling unit and a compute unit coupled to the task scheduling unit. The task scheduling unit performs a task dependency assessment of a task dependency graph and task data requirements that correspond to each task of the plurality of tasks. Based on the task dependency assessment, the task scheduling unit schedules a first task of the plurality of tasks and a second proxy object of a plurality of proxy objects specified by the task data requirements such that a memory transfer of the second proxy object of the plurality of proxy objects occurs while the first task is being executed.