公开(公告)号：US20150194879A1

公开(公告)日：2015-07-09

申请号：US14147228

申请日：2014-01-03

Applicant: Analog Devices Technology

Inventor： Roger Peppiette ,  Yanfeng Lu ,  Bin Shao ,  Linus Sheng

IPC: H02M3/07

CPC classification number: H02M3/073

Abstract: This application discusses, among other things apparatus and methods for a voltage boost circuit. In an example, a voltage boost circuit can include first and second inverters, sharing a first supply node, and sharing a second supply node, a first charge transfer capacitor, configured to couple a first clock signal to the first inverter output, a second charge transfer capacitor, configured to couple a second clock signal to the second inverter output, the second clock signal being out-of-phase with the first clock signal, a first gate drive capacitor, configured to couple the first clock signal to the second inverter input, and a second gate drive capacitor, configured to couple the second clock signal to the first inverter input.

Abstract translation: 本应用程序还讨论了升压电路的设备和方法。 在一个示例中，升压电路可以包括第一和第二反相器，共享第一电源节点，并共享第二电源节点，第一电荷转移电容器，被配置为将第一时钟信号耦合到第一反相器输出;第二充电 转移电容器，被配置为将第二时钟信号耦合到第二反相器输出，第二时钟信号与第一时钟信号异相;第一栅极驱动电容器，被配置为将第一时钟信号耦合到第二反相器输入 以及第二栅极驱动电容器，被配置为将所述第二时钟信号耦合到所述第一反相器输入。

公开(公告)号：US20150115923A1

公开(公告)日：2015-04-30

申请号：US14064490

申请日：2013-10-28

Applicant: Analog Devices Technology

Inventor： Bin Shao

IPC: H02M3/158 ,  H02M3/157

CPC classification number: H02M3/158 ,  H02M3/157 ,  H02M2001/0009

Abstract: A switching regulator or other apparatus or techniques can include load current monitoring to provide a digital representation of an estimated load current. Load current monitoring can be performed by a circuit including a counter circuit, a comparator circuit, and a digitally-controlled source coupled to the counter circuit and configured to adjust a bias condition of a sensing device in response to a count provided by the counter circuit in order to establish a proportional relationship between a current conducted by the sensing device and a corresponding current conducted by a power switching device. The counter circuit is configured to increment and decrement the count in response to information provided by the comparator output and the count is generally indicative of the estimated load current, such as an average load current.

Abstract translation: 开关调节器或其他装置或技术可以包括负载电流监视以提供估计负载电流的数字表示。 负载电流监视可以由包括计数器电路，比较器电路和耦合到计数器电路的数字控制源的电路执行，并且被配置为响应于由计数器电路提供的计数来调整感测装置的偏置条件 以便建立由感测装置传导的电流与由电力开关装置传导的对应电流之间的比例关系。 计数器电路被配置为响应于由比较器输出提供的信息而增加和减少计数，并且计数通常表示估计的负载电流，例如平均负载电流。

公开(公告)号：US20140282349A1

公开(公告)日：2014-09-18

申请号：US14028792

申请日：2013-09-17

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Roger Feng ,  Junxiao Chen ,  Bin Shao

IPC: G06F17/50

CPC classification number: G06F17/5063 ,  G06F2217/78

Abstract: A method can reuse at least one pin in demultiplexing (demuxing) a voltage from a pin. The method can be used to set an accurate current limit threshold in a design for test (DFT) phase and, thus, to accurately set a trimming code of a current limiter. The method uses the property that a power MOSFET has almost a same conductive resistance at a large drain current. Thus, the current limit threshold can be set according to an accurate drain-to-source voltage Vds at a small current sink that is less than a maximum current that ATE is able to provide. An accurate voltage Vds can be measured through Kelvin sensing drain and source pins of the power MOSFET, which are connected to a current sense circuit.

Abstract translation: 一种方法可以在从引脚解复用（解调））电压时重用至少一个引脚。 该方法可用于在测试（DFT）相位的设计中设置精确的电流限制阈值，从而准确地设置限流器的修整代码。 该方法使用功率MOSFET在大漏极电流下具有几乎相同的导电电阻的性质。 因此，可以根据小于ATE能够提供的最大电流的小电流宿的准确的漏极 - 源极电压Vds来设置电流限制阈值。 可以通过连接到电流检测电路的功率MOSFET的开尔文感测漏极和源极引脚来测量精确的电压Vds。

公开(公告)号：US20140253061A1

公开(公告)日：2014-09-11

申请号：US13789210

申请日：2013-03-07

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Shanshan Yang ,  Guoming Wu ,  Bin Shao

IPC: G05F1/46

CPC classification number: G05F1/46 ,  H02M1/36 ,  H02M3/158 ,  H02M2001/0032 ,  Y02B70/16

Abstract: A method and system to inhibit the switching of a current mode switching converter having high and low side switching elements coupled to an output inductor, the other end of which is coupled to an output node, and operated with respective modulated switching signals to regulate an output voltage Vout produced at the node. A current IC that varies with the difference between a reference voltage and a voltage proportional to Vout is compared with and a current IDETECT—PEAK which varies with the current conducted by the high side switching element; the result of the comparison of IC and IDETECT—PEAK is used to control the regulation of Vout during normal operation. Current IC is also compared with a current IDETECT—VALLEY which varies with the current conducted by the low side switching element. When IDETECT—VALLEY>IC, a ‘skip mode’ is triggered during which the switching signals are inhibited.

Abstract translation: 一种抑制具有耦合到输出电感器的高低侧开关元件的电流模式切换转换器的方法和系统，该输出电感器的另一端耦合到输出节点，并且用相应的调制开关信号进行操作，以调节输出 在节点处产生的电压Vout。 与参考电压和与Vout成比例的电压之间的差异变化的电流IC与当前由高侧开关元件传导的电流变化的IDETECT-PEAK进行比较; IC和IDETECT-PEAK的比较结果用于控制正常工作期间Vout的调节。 电流IC还与当前的IDETECT-VALLEY进行比较，其随着低侧开关元件所传导的电流而变化。 当IDETECT-VALLEY> IC时，触发切换信号的“跳过模式”。

公开(公告)号：US08941368B2

公开(公告)日：2015-01-27

申请号：US13789210

申请日：2013-03-07

Applicant: Analog Devices Technology

Inventor： Shanshan Yang ,  Guoming Wu ,  Bin Shao

IPC: G05F1/40 ,  G05F1/46

CPC classification number: G05F1/46 ,  H02M1/36 ,  H02M3/158 ,  H02M2001/0032 ,  Y02B70/16

Abstract: A method and system to inhibit the switching of a current mode switching converter having high and low side switching elements coupled to an output inductor, the other end of which is coupled to an output node, and operated with respective modulated switching signals to regulate an output voltage Vout produced at the node. A current IC that varies with the difference between a reference voltage and a voltage proportional to Vout is compared with and a current IDETECT—PEAK which varies with the current conducted by the high side switching element; the result of the comparison of IC and IDETECT—PEAK is used to control the regulation of Vout during normal operation. Current IC is also compared with a current IDETECT—VALLEY which varies with the current conducted by the low side switching element. When IDETECT—VALLEY>IC, a ‘skip mode’ is triggered during which the switching signals are inhibited.

Abstract translation: 一种抑制具有耦合到输出电感器的高低侧开关元件的电流模式切换转换器的方法和系统，该输出电感器的另一端耦合到输出节点，并且用相应的调制开关信号进行操作，以调节输出 在节点处产生的电压Vout。 与参考电压和与Vout成比例的电压之间的差异变化的电流IC与当前由高侧开关元件传导的电流变化的IDETECT-PEAK进行比较; IC和IDETECT-PEAK的比较结果用于控制正常工作期间Vout的调节。 电流IC还与当前的IDETECT-VALLEY进行比较，其随着低侧开关元件所传导的电流而变化。 当IDETECT-VALLEY> IC时，触发切换信号的“跳过模式”。

公开(公告)号：US08928303B2

公开(公告)日：2015-01-06

申请号：US13827666

申请日：2013-03-14

Applicant: Analog Devices Technology

Inventor： Zhijie Zhu ,  Junxiao Chen ,  Bin Shao

IPC: H02M3/156

CPC classification number: H02M3/156 ,  H02M2003/1566

Abstract: Apparatus and methods for generating a drive signal of a switching signal are disclosed. A first circuit receives an oscillating reference signal, a first compensation signal, a second compensation signal, and a third compensation signal. The first compensation signal is indicative of an error between an output voltage of a power converter and a reference voltage. The second compensation signal is indicative of the error relative to a threshold. The third compensation signal is indicative of an output current of the power converter. The first circuit generates a comparison signal having a waveform including pulses having durations based at least partly on a combination of the periodic reference signal, the first compensation signal, the second compensation signal, and the third compensation signal. A second circuit receives a clock signal and the comparison signal and generates a drive signal for activation and deactivation of a driver transistor.

Abstract translation: 公开了用于产生开关信号的驱动信号的装置和方法。 第一电路接收振荡参考信号，第一补偿信号，第二补偿信号和第三补偿信号。 第一补偿信号表示功率转换器的输出电压与参考电压之间的误差。 第二补偿信号指示相对于阈值的误差。 第三补偿信号表示功率转换器的输出电流。 第一电路产生具有波形的比较信号，该波形包括至少部分地基于周期性参考信号，第一补偿信号，第二补偿信号和第三补偿信号的组合的具有持续时间的脉冲。 第二电路接收时钟信号和比较信号并产生用于驱动晶体管的激活和去激活的驱动信号。

公开(公告)号：US09673696B2

公开(公告)日：2017-06-06

申请号：US14051702

申请日：2013-10-18

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Yanfeng Lu ,  Bin Shao

IPC: H02M1/36 ,  H02M3/155 ,  H02M3/07

CPC classification number: H02M1/36 ,  H02M3/07 ,  H02M3/155 ,  H03K2217/0081

Abstract: At least one embodiment provides a method for a nanopower boost regulator to startup from an ultra-low-voltage (such as 0.3V˜0.5V) for energy harvesting applications. The method does not necessarily require a special process or any external components such as mechanical switches. The startup circuit can include an asynchronous boost circuit to charge up an output with stacked power NMOS transistors, a ring oscillator, and/or a charge pump, along with accompanying circuitry.

公开(公告)号：US09531262B2

公开(公告)日：2016-12-27

申请号：US14147228

申请日：2014-01-03

Applicant: Analog Devices Technology

Inventor： Roger Peppiette ,  Yanfeng Lu ,  Bin Shao ,  Linus Sheng

IPC: G05F1/10 ,  G05F3/02 ,  H02M3/07

CPC classification number: H02M3/073

Abstract: This application discusses, among other things apparatus and methods for a voltage boost circuit. In an example, a voltage boost circuit can include first and second inverters, sharing a first supply node, and sharing a second supply node, a first charge transfer capacitor, configured to couple a first clock signal to the first inverter output, a second charge transfer capacitor, configured to couple a second clock signal to the second inverter output, the second clock signal being out-of-phase with the first clock signal, a first gate drive capacitor, configured to couple the first clock signal to the second inverter input, and a second gate drive capacitor, configured to couple the second clock signal to the first inverter input.

Abstract translation: 本应用程序还讨论了升压电路的设备和方法。 在一个示例中，升压电路可以包括第一和第二反相器，共享第一电源节点，并共享第二电源节点，第一电荷转移电容器，被配置为将第一时钟信号耦合到第一反相器输出;第二充电 转移电容器，被配置为将第二时钟信号耦合到第二反相器输出，第二时钟信号与第一时钟信号异相;第一栅极驱动电容器，被配置为将第一时钟信号耦合到第二反相器输入 以及第二栅极驱动电容器，被配置为将所述第二时钟信号耦合到所述第一反相器输入。

公开(公告)号：US20140268936A1

公开(公告)日：2014-09-18

申请号：US14051702

申请日：2013-10-18

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Yanfeng Lu ,  Bin Shao

IPC: H02M1/36

CPC classification number: H02M1/36 ,  H02M3/07 ,  H02M3/155 ,  H03K2217/0081

Abstract: At least one embodiment provides a method for a nanopower boost regulator to startup from an ultra-low-voltage (such as 0.3V˜0.5V) for energy harvesting applications. The method does not necessarily require a special process or any external components such as mechanical switches. The startup circuit can include an asynchronous boost circuit to charge up an output with stacked power NMOS transistors, a ring oscillator, and/or a charge pump, along with accompanying circuitry.

Abstract translation: 至少一个实施例提供了一种纳米功率升压调节器从能量收集应用的超低电压（例如0.3V〜0.5V）启动的方法。 该方法不一定需要特殊的过程或任何外部组件，例如机械开关。 启动电路可以包括异步升压电路，用于堆叠功率NMOS晶体管，环形振荡器和/或电荷泵以及相关电路对输出进行充电。

公开(公告)号：US08887119B2

公开(公告)日：2014-11-11

申请号：US14028792

申请日：2013-09-17

Applicant: Analog Devices Technology

Inventor： Roger Feng ,  Junxiao Chen ,  Bin Shao

IPC: G06F17/50

CPC classification number: G06F17/5063 ,  G06F2217/78

Abstract: A method can reuse at least one pin in demultiplexing (demuxing) a voltage from a pin. The method can be used to set an accurate current limit threshold in a design for test (DFT) phase and, thus, to accurately set a trimming code of a current limiter. The method uses the property that a power MOSFET has almost a same conductive resistance at a large drain current. Thus, the current limit threshold can be set according to an accurate drain-to-source voltage Vds at a small current sink that is less than a maximum current that ATE is able to provide. An accurate voltage Vds can be measured through Kelvin sensing drain and source pins of the power MOSFET, which are connected to a current sense circuit.

Abstract translation: 一种方法可以在从引脚解复用（解调））电压时重用至少一个引脚。 该方法可用于在测试（DFT）相位的设计中设置精确的电流限制阈值，从而准确地设置限流器的修整代码。 该方法使用功率MOSFET在大漏极电流下具有几乎相同的导电电阻的性质。 因此，可以根据小于ATE能够提供的最大电流的小电流宿的准确的漏极 - 源极电压Vds来设置电流限制阈值。 可以通过连接到电流检测电路的功率MOSFET的开尔文感测漏极和源极引脚来测量精确的电压Vds。