公开(公告)号：US11258947B2

公开(公告)日：2022-02-22

申请号：US16730859

申请日：2019-12-30

Applicant: Apple Inc.

Inventor： Sreeraman Anantharaman ,  Hyuck-Jae Lee ,  Vincent Wang

IPC: H04N5/232 ,  G06F3/14 ,  H04L29/08 ,  H04N7/01 ,  H04N5/225 ,  H04N7/10 ,  H04L69/324

Abstract: Methods and apparatus for link training and low power operation. A multi-lane high speed bus is optimized for transferring audio/visual (A/V) data at slower rates. In one embodiment, the high speed bus is configured to use a packet format structure that allows for more fluid data delivery times, thereby allowing the high speed bus to deliver A/V data at times selected to reduce power consumption. In another embodiment, the high speed bus is configured to cache link initialization data for subsequent link re-initialization before entering a low power state. Thereafter, when the link exits the low power state, the high speed bus can skip certain portions of link initialization. Still a third embodiment of the present disclosure is directed to exemplary modifications to existing high speed bus link training and low power operation, consistent with the aforementioned principles. Variants of a Universal Serial Bus implementation are provided for illustration.

公开(公告)号：US10523867B2

公开(公告)日：2019-12-31

申请号：US15620595

申请日：2017-06-12

Applicant: Apple Inc.

Inventor： Sreeraman Anantharaman ,  Hyuck-Jae Lee ,  Vincent Wang

IPC: H04N5/232 ,  G06F3/14 ,  H04L29/08 ,  H04N7/10 ,  H04N7/01 ,  H04N5/225

Abstract: Methods and apparatus for link training and low power operation. A multi-lane high speed bus is optimized for transferring audio/visual (A/V) data at slower rates. In one embodiment, the high speed bus is configured to use a packet format structure that allows for more fluid data delivery times, thereby allowing the high speed bus to deliver A/V data at times selected to reduce power consumption. In another embodiment, the high speed bus is configured to cache link initialization data for subsequent link re-initialization before entering a low power state. Thereafter, when the link exits the low power state, the high speed bus can skip certain portions of link initialization. Still a third embodiment of the present disclosure is directed to exemplary modifications to existing high speed bus link training and low power operation, consistent with the aforementioned principles. Variants of a Universal Serial Bus implementation are provided for illustration.

公开(公告)号：US20200213516A1

公开(公告)日：2020-07-02

申请号：US16730859

申请日：2019-12-30

Applicant: Apple Inc.

Inventor： Sreeraman Anantharaman ,  Hyuck-Jae Lee ,  Vincent Wang

IPC: H04N5/232 ,  H04N7/10 ,  H04N5/225 ,  H04N7/01 ,  H04L29/08 ,  G06F3/14

Abstract: Methods and apparatus for link training and low power operation. A multi-lane high speed bus is optimized for transferring audio/visual (A/V) data at slower rates. In one embodiment, the high speed bus is configured to use a packet format structure that allows for more fluid data delivery times, thereby allowing the high speed bus to deliver A/V data at times selected to reduce power consumption. In another embodiment, the high speed bus is configured to cache link initialization data for subsequent link re-initialization before entering a low power state. Thereafter, when the link exits the low power state, the high speed bus can skip certain portions of link initialization. Still a third embodiment of the present disclosure is directed to exemplary modifications to existing high speed bus link training and low power operation, consistent with the aforementioned principles. Variants of a Universal Serial Bus implementation are provided for illustration.

公开(公告)号：US20170359513A1

公开(公告)日：2017-12-14

申请号：US15620595

申请日：2017-06-12

Applicant: APPLE INC.

Inventor： Sreeraman Anantharaman ,  Hyuck-Jae Lee ,  Vincent Wang

IPC: H04N5/232 ,  H04N5/225 ,  H04N7/10 ,  H04N7/01 ,  H04L29/08

Abstract: Methods and apparatus for link training and low power operation. A multi-lane high speed bus is optimized for transferring audio/visual (A/V) data at slower rates. In one embodiment, the high speed bus is configured to use a packet format structure that allows for more fluid data delivery times, thereby allowing the high speed bus to deliver A/V data at times selected to reduce power consumption. In another embodiment, the high speed bus is configured to cache link initialization data for subsequent link re-initialization before entering a low power state. Thereafter, when the link exits the low power state, the high speed bus can skip certain portions of link initialization. Still a third embodiment of the present disclosure is directed to exemplary modifications to existing high speed bus link training and low power operation, consistent with the aforementioned principles. Variants of a Universal Serial Bus implementation are provided for illustration.