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公开(公告)号：US20190340998A1
公开(公告)日：2019-11-07
申请号：US16384716
申请日：2019-04-15
Applicant: Apple Inc.
Inventor： Yafei Bi , Lei He , Mohammad B. Vahid Far , Mir B. Ghaderi , Venu Madhav Duggineni , Vanessa C. Heppolette , Joshua P. De Cesare , Hyuck-Jae Lee
IPC: G09G5/00
Abstract: Systems, methods, and apparatus to transition a display device between operating modes using a single dedicated pin of a circuit connected to the display device. The dedicated pin can receive a packet signal corresponding to an operating mode for the display device, and the circuit can thereafter cause the display device to transition into the desired operating mode in response to receiving the packet signal. The operating mode can be a low power on mode where an interface connected to the circuit is deactivated and at least some circuitry of the display device is throttled or powered off. The display device can be driven in an all black state while in the low power on mode, thereby allowing the display device to more quickly transition out of the low power on mode compared to when the display device is completely off.
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公开(公告)号：US11258947B2
公开(公告)日：2022-02-22
申请号：US16730859
申请日：2019-12-30
Applicant: Apple Inc.
Inventor： Sreeraman Anantharaman , Hyuck-Jae Lee , Vincent Wang
Abstract: Methods and apparatus for link training and low power operation. A multi-lane high speed bus is optimized for transferring audio/visual (A/V) data at slower rates. In one embodiment, the high speed bus is configured to use a packet format structure that allows for more fluid data delivery times, thereby allowing the high speed bus to deliver A/V data at times selected to reduce power consumption. In another embodiment, the high speed bus is configured to cache link initialization data for subsequent link re-initialization before entering a low power state. Thereafter, when the link exits the low power state, the high speed bus can skip certain portions of link initialization. Still a third embodiment of the present disclosure is directed to exemplary modifications to existing high speed bus link training and low power operation, consistent with the aforementioned principles. Variants of a Universal Serial Bus implementation are provided for illustration.
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公开(公告)号：US10777106B2
公开(公告)日：2020-09-15
申请号：US15717755
申请日：2017-09-27
Applicant: Apple Inc.
Inventor： Hung Sheng Lin , Jie Won Ryu , Kingsuk Brahma , Hyunwoo Nho , Baris Cagdaser , Junhua Tan , Sun-Il Chang , Luigi Panseri , Injae Hwang , Jesse A. Richmond , Toshiaki Sawada , Hyuck-Jae Lee
IPC: G09G3/00 , G09G3/3275 , G09G3/36 , G09G3/3225
Abstract: An electronic device includes a display having a number of pixels, source driving circuitry that drives data to the pixels, and data lines that communicatively couple the source driving circuitry with the pixels. The electronic device also includes quality monitoring and calibration circuitry that identifies degradation in the source driving circuitry, one or more of the data lines, or both. The electronic device may be controlled based at least in part upon identification of the degradation.
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公开(公告)号：US10943557B2
公开(公告)日：2021-03-09
申请号：US16384716
申请日：2019-04-15
Applicant: Apple Inc.
Inventor： Yafei Bi , Lei He , Mohammad B. Vahid Far , Mir B. Ghaderi , Venu Madhav Duggineni , Vanessa C. Heppolette , Joshua P. De Cesare , Hyuck-Jae Lee
IPC: G09G5/00
Abstract: Systems, methods, and apparatus to transition a display device between operating modes using a single dedicated pin of a circuit connected to the display device. The dedicated pin can receive a packet signal corresponding to an operating mode for the display device, and the circuit can thereafter cause the display device to transition into the desired operating mode in response to receiving the packet signal. The operating mode can be a low power on mode where an interface connected to the circuit is deactivated and at least some circuitry of the display device is throttled or powered off. The display device can be driven in an all black state while in the low power on mode, thereby allowing the display device to more quickly transition out of the low power on mode compared to when the display device is completely off.
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Patent Agency Ranking
5.发明申请公开(公告)号：US20170359513A1
公开(公告)日：2017-12-14
申请号：US15620595
申请日：2017-06-12
Applicant: APPLE INC.
Inventor： Sreeraman Anantharaman , Hyuck-Jae Lee , Vincent Wang
Abstract: Methods and apparatus for link training and low power operation. A multi-lane high speed bus is optimized for transferring audio/visual (A/V) data at slower rates. In one embodiment, the high speed bus is configured to use a packet format structure that allows for more fluid data delivery times, thereby allowing the high speed bus to deliver A/V data at times selected to reduce power consumption. In another embodiment, the high speed bus is configured to cache link initialization data for subsequent link re-initialization before entering a low power state. Thereafter, when the link exits the low power state, the high speed bus can skip certain portions of link initialization. Still a third embodiment of the present disclosure is directed to exemplary modifications to existing high speed bus link training and low power operation, consistent with the aforementioned principles. Variants of a Universal Serial Bus implementation are provided for illustration.
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6.发明申请公开(公告)号：US20200213516A1
公开(公告)日：2020-07-02
申请号：US16730859
申请日：2019-12-30
Applicant: Apple Inc.
Inventor： Sreeraman Anantharaman , Hyuck-Jae Lee , Vincent Wang
Abstract: Methods and apparatus for link training and low power operation. A multi-lane high speed bus is optimized for transferring audio/visual (A/V) data at slower rates. In one embodiment, the high speed bus is configured to use a packet format structure that allows for more fluid data delivery times, thereby allowing the high speed bus to deliver A/V data at times selected to reduce power consumption. In another embodiment, the high speed bus is configured to cache link initialization data for subsequent link re-initialization before entering a low power state. Thereafter, when the link exits the low power state, the high speed bus can skip certain portions of link initialization. Still a third embodiment of the present disclosure is directed to exemplary modifications to existing high speed bus link training and low power operation, consistent with the aforementioned principles. Variants of a Universal Serial Bus implementation are provided for illustration.
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公开(公告)号：US10523867B2
公开(公告)日：2019-12-31
申请号：US15620595
申请日：2017-06-12
Applicant: Apple Inc.
Inventor： Sreeraman Anantharaman , Hyuck-Jae Lee , Vincent Wang
Abstract: Methods and apparatus for link training and low power operation. A multi-lane high speed bus is optimized for transferring audio/visual (A/V) data at slower rates. In one embodiment, the high speed bus is configured to use a packet format structure that allows for more fluid data delivery times, thereby allowing the high speed bus to deliver A/V data at times selected to reduce power consumption. In another embodiment, the high speed bus is configured to cache link initialization data for subsequent link re-initialization before entering a low power state. Thereafter, when the link exits the low power state, the high speed bus can skip certain portions of link initialization. Still a third embodiment of the present disclosure is directed to exemplary modifications to existing high speed bus link training and low power operation, consistent with the aforementioned principles. Variants of a Universal Serial Bus implementation are provided for illustration.
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公开(公告)号：US10262622B2
公开(公告)日：2019-04-16
申请号：US15260580
申请日：2016-09-09
Applicant: Apple Inc.
Inventor： Yafei Bi , Lei He , Mohammad B. Vahid Far , Mir B. Ghaderi , Venu Madhav Duggineni , Vanessa C. Heppolette , Joshua P. De Cesare , Hyuck-Jae Lee
IPC: G09G5/00
Abstract: This application relates to systems, methods, and apparatus for transitioning a display device between operating modes using a single dedicated pin of a circuit connected to the display device. The dedicated pin can receive a packet signal corresponding to an operating mode for the display device, and the circuit can thereafter cause the display device to transition into the desired operating mode in response to receiving the packet signal. The operating mode can be a low power on mode where an interface connected to the circuit is deactivated and at least some circuitry of the display device is throttled or powered off. The display device can be driven in an all black state while in the low power on mode, thereby allowing the display device to more quickly transition out of the low power on mode compared to when the display device is completely off.
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公开(公告)号：US20190096300A1
公开(公告)日：2019-03-28
申请号：US15717755
申请日：2017-09-27
Applicant: Apple Inc.
Inventor： Hung Sheng Lin , Jie Won Ryu , Kingsuk Brahma , Hyunwoo Nho , Baris Cagdaser , Junhua Tan , Sun-Il Chang , Luigi Panseri , Injae Hwang , Jesse A. Richmond , Toshiaki Sawada , Hyuck-Jae Lee
IPC: G09G3/00
Abstract: An electronic device includes a display having a number of pixels, source driving circuitry that drives data to the pixels, and data lines that communicatively couple the source driving circuitry with the pixels. The electronic device also includes quality monitoring and calibration circuitry that identifies degradation in the source driving circuitry, one or more of the data lines, or both. The electronic device may be controlled based at least in part upon identification of the degradation.
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