公开(公告)号：US20180364980A1

公开(公告)日：2018-12-20

申请号：US15626454

申请日：2017-06-19

Applicant: ARM Limited

Inventor： Daniel ARULRAJ ,  Graeme Peter BARNES ,  Lee EISEN ,  Gary GORMAN

IPC: G06F7/50 ,  G06F3/06 ,  G06F12/14

CPC classification number: G06F7/50 ,  G06F3/0622 ,  G06F3/0638 ,  G06F3/0673 ,  G06F7/02 ,  G06F12/1416 ,  G06F2212/1052 ,  H03M7/24 ,  H03M7/30 ,  H03M7/3066 ,  H03M7/3091 ,  H03M7/702

Abstract: A data processing apparatus is provided, for performing a determination of whether a value falls within a boundary defined by a lower limit between 0 and 2m and an upper limit between 0 and 2m. The apparatus includes storage circuitry that stores each of the lower limit and the upper limit in a compressed form as a mantissa of q

公开(公告)号：US20200042464A1

公开(公告)日：2020-02-06

申请号：US16055240

申请日：2018-08-06

Applicant: Arm Limited

Inventor： Daniel ARULRAJ ,  Lee Evan EISEN ,  Graeme Peter BARNES

IPC: G06F12/14 ,  G06F9/30

Abstract: An apparatus and method are provided for comparing regions associated with first and second bounded pointers to determine whether the region defined for the second bounded pointer is a subset of the region defined for the first bounded pointer. Each bounded pointer has a pointer value and associated upper and lower limits identifying the memory region for that bounded pointer. The apparatus stores first and second bounded pointer representations, each representation comprising a pointer value having p bits, and identifying the upper and lower limits in a compressed form by identifying a lower limit mantissa of q bits, an upper limit mantissa of q bits and an exponent value e. A most significant p−q−e bits of the lower limit and the upper limit is derivable from the most significant p−q−e bits of the pointer value. Mapping circuitry is used to map the lower limit mantissas and upper limit mantissas of the first and second bounded pointer representations to a q+x bit address space comprising 2x regions of size 2n1, where n1 is the value of n determined when using the exponent value of the first bounded pointer representation. Mantissa extension circuitry extends the lower limit and upper limit mantissas for each bounded pointer representation to create extended lower limit and upper limit mantissas comprising q+x bits, where a most significant x bits of each extended limit mantissa are mapping bits identifying which region the associated limit mantissa is mapped to. The determination circuitry then determines whether the region for the second pointer is a subset of the region for the first bounded pointer by comparing the extended lower and upper limit mantissas.

公开(公告)号：US20180046460A1

公开(公告)日：2018-02-15

申请号：US15236769

申请日：2016-08-15

Applicant: ARM LIMITED

Inventor： Gary Alan GORMAN ,  Lee Evan EISEN ,  Neil BURGESS ,  Daniel ARULRAJ

IPC: G06F9/30

Abstract: Data processing apparatus comprises: processing circuitry to selectively apply vector processing operations to one or more data items of one or more data vectors each comprising a plurality of data items at respective vector positions in the data vector, according to the state of respective predicate indicators associated with the vector positions; a predicate store; and predicate generation circuitry to apply a processing operation to generate a set of predicate indicators, each associated with a respective one of the vector positions, to generate a count value indicative of the number of predicate indicators in the set having a given state, and to store the generated set of predicate indicators and the count value in the predicate store.

公开(公告)号：US20180046459A1

公开(公告)日：2018-02-15

申请号：US15236728

申请日：2016-08-15

Applicant: ARM LIMITED

Inventor： Neil BURGESS ,  Lee Evan EISEN ,  Gary Alan GORMAN ,  Daniel ARULRAJ

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/30018 ,  G06F9/30072 ,  G06F9/3013

Abstract: Data processing apparatus comprises processing circuitry to selectively apply vector processing operations to one or more data items of one or more data vectors each comprising an ordered plurality of data items at respective vector positions in the data vector, according to the state of respective predicate indicators associated with the vector positions; predicate generation circuitry to apply a processing operation to generate an ordered set of predicate indicators, each associated with a respective one of the vector positions, the ordered set of predicate indicators being associated with an ordered set of active indicators each having an active or an inactive state; and a detector to detect a status flag indicative of whether a predicate indicator at a position, in the ordered set of predicate indicators, corresponding to the position of an outermost active indicator having the active state, has a given state; in which the detector comprises: first and second circuitry to combine the ordered set of predicate indicators and the ordered set of active indicators using first and second respective logical bit-wise combinations to generate first and second ordered sets of intermediate data; and arithmetic circuitry to combine the first and second ordered sets of intermediate data using an arithmetic combination generating a carry bit, the detector generating the status flag in dependence upon the carry bit.