-
公开(公告)号：US20210342248A1
公开(公告)日：2021-11-04
申请号：US17271399
申请日：2019-08-30
Applicant: Arm Limited
Inventor： Timothy HAYES , Giacomo GABRIELLI , Matthew James HORSNELL
Abstract: An apparatus and method are provided for monitoring events in a data processing system. The apparatus has first event monitoring circuitry for monitoring occurrences of a first event within a data processing system, and for asserting a first signal to indicate every m-th occurrence of the first event, where m is an integer of 1 or more. In addition second event monitoring circuitry is used to monitor occurrences of a second event within the data processing system, and to assert a second signal to indicate every n-th occurrence of the second event, where n is an integer of 1 or more. History maintenance circuitry then maintains event history information which is updated in dependence on the asserted first and second signals. Further, history analysis circuitry is responsive to an analysis trigger to analyse the event history information in order to detect a reporting condition when the event history information indicates that a ratio between occurrences of the first event and the occurrences of the second event is outside an acceptable range. The history analysis circuitry is then responsive to detection of the reporting condition to assert a report signal. This provides a particularly efficient and effective mechanism for monitoring ratios of events within a data processing system.
-
公开(公告)号：US20190258489A1
公开(公告)日：2019-08-22
申请号：US16331179
申请日：2017-08-14
Applicant: ARM LIMITED
Inventor： Matthew James HORSNELL , Mbou EYOLE
Abstract: An apparatus has processing circuitry supporting vector load and store instructions. In response to a transaction start event, the processing circuitry executes one or more subsequent instructions speculatively. In response to a transaction end event, the processing circuitry commits speculative results of those instructions. Hazard detection circuitry detects whether an inter-element address hazard occurs between an address for data element J for an earlier vector load instruction and an address for data element K for a later vector store instruction, where K and J are not equal. In response to detecting the inter-element address hazard, the hazard detection circuitry triggers the processing circuitry to abort further processing of the instructions following the transaction start event and to prevent the speculative results being committed. This approach can provide faster performance for vectorised code.
-
公开(公告)号：US20130132737A1
公开(公告)日：2013-05-23
申请号：US13627209
申请日：2012-09-26
Applicant: ARM LIMITED
CPC classification number: G06F21/602 , G06F9/30007 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30145 , G06F9/3887 , G09C1/00 , H04L9/0643 , H04L9/3239 , H04L2209/12 , H04L2209/125
Abstract: A data processing system 2 includes a single instruction multiple data register file 12 and single instruction multiple processing circuitry 14. The single instruction multiple data processing circuitry 14 supports execution of cryptographic processing instructions for performing parts of a hash algorithm. The operands are stored within the single instruction multiple data register file 12. The cryptographic support instructions do not follow normal lane-based processing and generate output operands in which the different portions of the output operand depend upon multiple different elements within the input operand.
-
4.发明申请公开(公告)号：US20200278882A1
公开(公告)日：2020-09-03
申请号：US16651017
申请日：2018-08-21
Applicant: Arm Limited
Inventor： Matthew James HORSNELL , Grigorios MAGKLIS , Richard Roy GRISENTHWAITE , Stephan DIESTELHORST
Abstract: A data processing apparatus has processing circuitry with transactional memory support circuitry to support execution of a transaction using transactional memory. In response to an exception mask updating instruction which updates exception mask information to enable at least one subset of exceptions which was disabled at the start of processing of a transaction, the processing circuitry permits un-aborted processing of one or more subsequent instruction of the transaction that follow the exception mask update instruction.
-
公开(公告)号：US20170161112A1
公开(公告)日：2017-06-08
申请号：US15324082
申请日：2015-06-11
Applicant: ARM LIMITED
Inventor： Matthew James HORSNELL , Stephan DIESTELHORST
IPC: G06F9/50
Abstract: A data processing apparatus comprises a plurality of data storage elements, each configured to store data. Mask storage circuitry stores a mask and processing circuitry executes one or more instructions. A data saver is configured, in response to a transactional start instruction, to select a subset of the data storage elements and to save a backup of the subset of the data storage elements. Mask control circuitry then updates the mask to indicate the subset of the data storage elements selected by the data saver. Finally, a monitor detects write or write attempts made to one of the data storage elements not indicated by the mask. Accordingly, a user need not save all data storage elements (e.g. registers) in a system or specify precisely which data storage elements must be saved in order to perform a transaction. Instead, the set of data storage elements that must be saved can be determined and specified dynamically, and the system can respond if an attempt is made to write to a data storage element that has not been saved or backed up.
-
Patent Agency Ranking
公开(公告)号：US20170161095A1
公开(公告)日：2017-06-08
申请号：US15325301
申请日：2015-06-09
Applicant: ARM LIMITED
Inventor： Matthew James HORSNELL , Stephan DIESTELHORST
IPC: G06F9/46 , G06F12/128 , G06F12/0891 , G06F12/0875
CPC classification number: G06F9/467 , G06F9/528 , G06F12/0811 , G06F12/0875 , G06F12/0891 , G06F12/128 , G06F2212/1032 , G06F2212/451 , G06F2212/621
Abstract: A data processing apparatus and method of data processing are provided, which relate to the operation of a processor which maintains a push call stack in dependence on the data processing instructions executed. The processor is configured to operate in a transactional execution mode when the data processing instructions seek access to a stored data item which is shared with a further processor. When the processor enters its transactional execution mode it stores a copy of the current stack depth indication and thereafter, when operating in its transactional execution mode, further modifications to the call stack are compared to the copy of the stack depth indication stored. If the relative stacking position of the required modification is in a positive stack growth direction with respect to the copy stored, the modification to the call stack is labelled as non-speculative. Conversely if the modification to the call stack is to be made at a relative stacking position which is not in a positive growth direction with respect to the position indicated by the copy stored, then that modification is labelled as speculative. The size of the write-set associated with maintaining the call stack whilst in transactional execution mode can therefore be reduced.
-
公开(公告)号：US20210271485A1
公开(公告)日：2021-09-02
申请号：US17269216
申请日：2019-10-17
Applicant: Arm Limited
Inventor： Matthew James HORSNELL , Richard Roy GRISENTHWAITE
Abstract: In an apparatus with transactional memory support circuitry, for a first type of transaction started using a first type of transaction start instruction, commitment of results of instructions executed speculatively following the first type of transaction start instruction are prevented until a transaction end instruction is reached. An abort is triggered when a conflict is detected between an address of a memory access from another thread and the addresses tracked for the transaction. For a second type of transaction started using a second type of transaction start instruction, an address of the read operation is marked as trackable whilst an address of a write operation is omitted from being marked as trackable. This allows an apparatus that supports transactional memory to also be used for multi-word address watching.
-
8.发明申请公开(公告)号：US20200272505A1
公开(公告)日：2020-08-27
申请号：US16651178
申请日：2018-08-30
Applicant: ARM Limited
Inventor： Matthew James HORSNELL , Stephan DIESTELHORST
Abstract: In an apparatus (2) with transactional memory support, a predetermined type of transaction start instruction or a subsequent instruction following the predetermined type of transaction start instruction triggers capture of a lock identifier which identifies a lock variable for controlling exclusive access to at least one resource. In response to a predetermined type of transaction end instruction which follows the predetermined type of transaction start instruction, the lock variable is checked and commitment of results of speculatively executed instructions of the transaction is prevented or deferred when the lock variable indicates that another thread holds the exclusive access to the target resource. This approach can improve performance when executing transactions in a transactional memory based system.
-
公开(公告)号：US20190205140A1
公开(公告)日：2019-07-04
申请号：US16208701
申请日：2018-12-04
Applicant: Arm Limited
Inventor： Richard Roy GRISENTHWAITE , Giacomo GABRIELLI , Matthew James HORSNELL
IPC: G06F9/30
CPC classification number: G06F9/30196 , G06F9/30018 , G06F9/30032 , G06F9/30036
Abstract: An apparatus comprises processing circuitry to perform data processing and instruction decoding circuitry to decode instructions to control the processing circuitry to perform the data processing. The instruction decoding circuitry is responsive to a speculation barrier instruction to control the processing circuitry to prevent a subsequent operation, appearing in program order after the speculation barrier instruction, that has an address dependency on an earlier instruction preceding the speculation barrier instruction in the program order, from speculatively influencing allocations of entries in a cache. This provides protection against speculative cache-timing side-channel attacks.
-
公开(公告)号：US20170329627A1
公开(公告)日：2017-11-16
申请号：US15537015
申请日：2015-11-24
Applicant: ARM LIMITED
Inventor： Stephan DIESTELHORST , Matthew James HORSNELL
CPC classification number: G06F9/467 , G06F9/3842 , G06F11/362
Abstract: An apparatus (2) may have a processing element (4) for performing data access operations to access data from at least one storage device (10, 12, 14). The processing element may have at least one transactional processing resource (10, 18) supporting processing of a transaction in which data accesses are performed speculatively following a transaction start event and for which the speculative results are committed in response to a transaction end event. Monitoring circuitry (30) captures monitoring data indicating a degree of utilization of the transactional processing resource (10, 18) when processing the transaction.
-
-
-
-
-
-
-
-
-
Search Results
24
records
(took 0.016 seconds)
