公开(公告)号：US20180122709A1

公开(公告)日：2018-05-03

申请号：US15796593

申请日：2017-10-27

Applicant: ASM IP Holding B.V.

Inventor： Qi Xie ,  Michael Eugen Givens ,  Petri Raisanen ,  Jan Willem Maes

IPC: H01L21/8238 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/285 ,  H01L27/092 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L21/823842 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/28088 ,  H01L21/28556 ,  H01L21/32133 ,  H01L21/823821 ,  H01L21/823857 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78

Abstract: Methods for forming a semiconductor device and related semiconductor device structures are provided. In some embodiments, methods may include forming an NMOS gate dielectric and a PMOS gate dielectric over a substrate and forming a first work function metal over the NMOS gate dielectric and over the PMOS gate dielectric. In some embodiments, methods may also include, removing the first work function metal over the NMOS gate dielectric and forming a second work function metal over the NMOS gate dielectric and over the PMOS gate dielectric. In some embodiments, related semiconductor device structures may include an NMOS gate dielectric and a PMOS gate dielectric disposed over a semiconductor substrate. A PMOS gate electrode may be disposed over the PMOS gate dielectric and the PMOS gate electrode may include a first work function metal disposed over the PMOS gate dielectric and a second work function metal disposed over the first work function metal. A NMOS gate electrode may be disposed over the NMOS gate dielectric and the NMOS gate electrode may include the second work function metal.