公开(公告)号：US12132089B2

公开(公告)日：2024-10-29

申请号：US17866739

申请日：2022-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/285 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/40 ,  H01L29/45 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/823475 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7853 ,  H01L21/02063 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/76819 ,  H01L21/7684 ,  H01L21/823425 ,  H01L21/823431 ,  H01L29/045 ,  H01L29/1045 ,  H01L29/165 ,  H01L29/45 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L2029/7858

Abstract: Embodiments disclosed herein relate generally to methods for forming recesses in epitaxial source/drain regions for forming conductive features. In some embodiments, the recesses are formed in a two-step etching process including an anisotropic etch to form a vertical opening and an isotropic etch to expand an end portion of the vertical opening laterally and vertically. The recesses can have increased contact area between the source/drain region and the conductive feature, and can enable reduced resistance therebetween.

公开(公告)号：US20240355499A1

公开(公告)日：2024-10-24

申请号：US18641543

申请日：2024-04-22

Applicant: Samsung Electronics Co., Ltd. ,  UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： CHANG SEOK LEE ,  Yohan KIM ,  Hyung-Joon SHIN ,  KYUNGEUN BYUN ,  KEUN WOOK SHIN ,  HYEON JIN SHIN ,  Seungwoo SON ,  Zonghoon LEE

IPC: H01B1/04 ,  C23C16/26 ,  C23C16/50 ,  H01L21/285 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532 ,  H01L25/065

CPC classification number: H01B1/04 ,  H01L21/76885 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53276 ,  C23C16/26 ,  C23C16/50 ,  H01L21/28556 ,  H01L25/0657 ,  H01L2225/06541 ,  H01L2225/06565

Abstract: Spiral graphene nanocrystals having electrical conductivity in a vertical direction due to interlayer covalent bonds, a graphene thin film including the spiral graphene nanocrystals, an interconnect structure manufactured from the spiral graphene nanocrystals or the graphene thin film, and a method of manufacturing the interconnect structure and an electronic device including the interconnect structure.

公开(公告)号：US12112973B2

公开(公告)日：2024-10-08

申请号：US17456009

申请日：2021-11-22

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Tao Li

IPC: H01L21/762 ,  H01L21/285

CPC classification number: H01L21/76224 ,  H01L21/28556

Abstract: The embodiment of the present invention provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises: a substrate having a trench therein; a first layer covering the bottom and the sidewall of the trench; and a second layer covering the surface of the first layer, wherein the step coverage of the second layer is different from the step coverage of the first layer. The embodiment of the invention is conducive to obtaining a multi-layer structure with preset step coverage.

公开(公告)号：US12084757B2

公开(公告)日：2024-09-10

申请号：US17891449

申请日：2022-08-19

Applicant: KOKUSAI ELECTRIC CORPORATION

Inventor： Arito Ogawa ,  Atsuro Seino

IPC: C23C16/02 ,  C23C16/18 ,  C23C16/455 ,  H01L21/285

CPC classification number: C23C16/0281 ,  C23C16/18 ,  C23C16/45527 ,  C23C16/45553 ,  H01L21/28556 ,  H01L21/28568

Abstract: There are included (a) supplying a gas containing an organic ligand to a substrate; (b) supplying a metal-containing gas to the substrate; and (c) supplying a first reducing gas to the substrate, wherein after (a), a metal-containing film is formed on the substrate by performing (b) and (c) one or more times, respectively.

公开(公告)号：US20240258380A1

公开(公告)日：2024-08-01

申请号：US18636310

申请日：2024-04-16

Applicant: ROHM CO., LTD.

Inventor： Tsunenobu KIMOTO ,  Takuma KOBAYASHI ,  Yuki NAKANO ,  Masatoshi AKETA

IPC: H01L29/16 ,  H01L21/02 ,  H01L21/285 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/1608 ,  H01L21/02238 ,  H01L21/02614 ,  H01L21/28556 ,  H01L29/0607 ,  H01L29/4236 ,  H01L29/66045

Abstract: A semiconductor device includes a SiC semiconductor layer that has a carbon density of 1.0×1022 cm−3 or more, a SiO2 layer that is formed on the SiC semiconductor layer and that has a connection surface contiguous to the SiC semiconductor layer and a non-connection surface positioned on a side opposite to the connection surface, a carbon-density-decreasing region that is formed at a surface layer portion of the connection surface of the SiO2 layer and in which a carbon density gradually decreases toward the non-connection surface of the SiO2 layer, and a low carbon density region that is formed at a surface layer portion of the non-connection surface of the SiO2 layer and that has a carbon density of 1.0×1019 cm−3 or less.

公开(公告)号：US20240213304A1

公开(公告)日：2024-06-27

申请号：US18107521

申请日：2023-02-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Fu-Yu Tsai ,  Chung-Yi Chiu

IPC: H01L27/06 ,  H01L21/285 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L28/60 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L27/0629 ,  H01L27/0647

Abstract: An MIM capacitor structure includes numerous inter-metal dielectrics. A trench is embedded within the inter-metal dielectrics. A capacitor is disposed within the trench. The capacitor includes a first electrode layer, a capacitor dielectric layer and a second electrode layer. The first electrode layer, the capacitor dielectric layer and the second electrode layer fill in and surround the trench. The capacitor dielectric layer is between the first electrode layer and the second electrode layer. A silicon oxide liner surrounds a sidewall of the trench and contacts the first electrode layer.

公开(公告)号：US12018374B2

公开(公告)日：2024-06-25

申请号：US16813175

申请日：2020-03-09

Applicant: DSGI Technologies, Inc.

Inventor： Jeffrey Edward Kowalski

IPC: C23C16/511 ,  C23C16/458 ,  H01J37/32 ,  H01L21/02 ,  H01L21/285

CPC classification number: C23C16/511 ,  C23C16/4588 ,  H01J37/32192 ,  H01J37/32201 ,  H01J37/32211 ,  H01J37/3222 ,  H01J37/32266 ,  H01J37/32357 ,  H01J37/32715 ,  H01J37/32733 ,  H01J37/32816 ,  H01L21/02247 ,  H01L21/02274 ,  H01L21/28556 ,  H01J2237/3321

Abstract: Systems and methods of forming a thin film on substrate includes positioning the substrate in a chamber; generating, via a uniform microwave field generator, a microwave field around the substrate; and guiding radicals into the chamber so that plasma is generated about the substrate to form the thin film on the substrate.

公开(公告)号：US11970772B2

公开(公告)日：2024-04-30

申请号：US17451534

申请日：2021-10-20

Applicant: Lam Research Corporation

Inventor： Purushottam Kumar ,  Adrien LaVoie ,  Jun Qian ,  Hu Kang ,  Ishtak Karim ,  Fung Suong Ou

IPC: C23C16/455 ,  C23C16/52 ,  H01L21/02 ,  H01L21/285

CPC classification number: C23C16/45527 ,  C23C16/45561 ,  C23C16/52 ,  H01L21/0228 ,  H01L21/0262 ,  H01L21/28556

Abstract: Methods and apparatuses for controlling precursor flow in a semiconductor processing tool are disclosed. A method may include flowing gas through a gas line, opening an ampoule valve(s), before a dose step, to start a flow of precursor from the ampoule to a process chamber through the gas line, closing the ampoule valve(s) to stop the precursor from flowing out of the ampoule, opening a process chamber valve, at the beginning of the dose step, to allow the flow of precursor to enter the process chamber, and closing the process chamber valve, at the end of the dose step, to stop the flow of precursor from entering the process chamber. A controller may include at least one memory and at least one processor and the at least one memory may store instructions for controlling the at least one processor to control precursor flow in a semiconductor processing tool.

公开(公告)号：US20240136191A1

公开(公告)日：2024-04-25

申请号：US18402018

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Hsiu Hung ,  Chien Chang ,  Yi-Hsiang Chao ,  Hung-Yi Huang ,  Chih-Wei Chang

IPC: H01L21/285 ,  H01L21/02 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/28518 ,  H01L21/02274 ,  H01L21/28556 ,  H01L21/76802 ,  H01L21/76879 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a semiconductor device includes forming source/drain regions on opposing sides of a gate structure, where the gate structure is over a fin and surrounded by a first dielectric layer; forming openings in the first dielectric layer to expose the source/drain regions; selectively forming silicide regions in the openings on the source/drain regions using a plasma-enhanced chemical vapor deposition (PECVD) process; and filling the openings with an electrically conductive material.

公开(公告)号：US11948775B2

公开(公告)日：2024-04-02

申请号：US17979180

申请日：2022-11-02

Applicant: ASM America, Inc.

Inventor： Imran Ahmed Bhutta

IPC: H03H7/40 ,  H01J37/32 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/67 ,  H03H7/38

CPC classification number: H01J37/32183 ,  H01L21/02274 ,  H01L21/28556 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32136 ,  H01L21/67069 ,  H03H7/38 ,  H03H7/40 ,  H01J2237/332 ,  H01J2237/334

Abstract: In one embodiment, a method of matching an impedance is disclosed. An impedance matching network is coupled between a radio frequency (RF) source and a plasma chamber. The matching network includes a variable reactance element (VRE) having different positions for providing different reactances. The RF source is subject to a power control scheme to control a power delivered to the matching network. Based on a determined parameter, a new position for the VRE is determined to reduce a reflected power at the RF input of the matching network. The VRE is altered to the new position while the power control scheme is altered.