公开(公告)号：US06690240B2

公开(公告)日：2004-02-10

申请号：US10043558

申请日：2002-01-10

申请人： Adrian Maxim ,  Baker Scott, III ,  Edmund M. Schneider ,  Melvin L. Hagge

发明人： Adrian Maxim ,  Baker Scott, III ,  Edmund M. Schneider ,  Melvin L. Hagge

IPC分类号： H03L700

CPC分类号： H03L7/0893 ,  H03L7/093 ,  H03L7/18

摘要： A loop filter device and method for implementing a loop filter for a phase locked loop (“PLL”) circuit, which locks a frequency of a signal to a reference frequency, are disclosed. The loop filter includes a proportional path circuit and an integral path circuit. The proportional path circuit receives a charge pump output and determines and holds a charge to be directed to or taken from a PLL circuit throughout an update period based on a detected phase difference for the update period for locking a frequency of a signal for a PLL circuit to a reference frequency. The integral path circuit is coupled to the proportional path circuit, and the integral path circuit receives another charge pump output and tracks a total charge level for the PLL circuit based on phase differences for present and prior update periods.

摘要翻译： 公开了一种用于实现将信号的频率锁定到参考频率的锁相环（“PLL”）电路的环路滤波器的环路滤波器装置和方法。 环路滤波器包括比例路径电路和积分路径电路。 比例路径电路接收电荷泵输出，并且基于用于锁定PLL电路的信号的频率的更新周期的检测到的相位差来确定并保持在整个更新周期期间被引导到PLL电路或从PLL电路获取的电荷 到参考频率。 积分路径电路耦合到比例路径电路，并且积分路径电路接收另一个电荷泵输出，并且基于当前和先前更新周期的相位差来跟踪PLL电路的总电荷电平。

公开(公告)号：US06828864B2

公开(公告)日：2004-12-07

申请号：US10612200

申请日：2003-07-03

申请人： Adrian Maxim ,  Baker Scott, III ,  Edmund M. Schneider ,  Melvin L. Hagge

发明人： Adrian Maxim ,  Baker Scott, III ,  Edmund M. Schneider ,  Melvin L. Hagge

IPC分类号： H03L700

CPC分类号： H03L7/0893 ,  H03L7/093 ,  H03L7/18

摘要： A loop filter device and method for implementing a loop filter for a phase locked loop (“PLL”) circuit, which locks a frequency of a signal to a reference frequency, are disclosed. The loop filter includes a proportional path circuit and an integral path circuit. The proportional path circuit receives a charge pump output and determines and holds a charge to be directed to or taken from a PLL circuit throughout an update period based on a detected phase difference for the update period for locking a frequency of a signal for a PLL circuit to a reference frequency. The integral path circuit is coupled to the proportional path circuit, and the integral path circuit receives another charge pump output and tracks a total charge level for the PLL circuit based on phase differences for present and prior update periods.

公开(公告)号：US6081783A

公开(公告)日：2000-06-27

申请号：US970979

申请日：1997-11-14

申请人： James Divine ,  Jeffrey Niehaus ,  Miroslav Dokic ,  Raghunath Rao ,  Terry Ritchie ,  Baker Scott, III ,  John Pacourek ,  Zheng Luo

发明人： James Divine ,  Jeffrey Niehaus ,  Miroslav Dokic ,  Raghunath Rao ,  Terry Ritchie ,  Baker Scott, III ,  John Pacourek ,  Zheng Luo

IPC分类号： H03M7/30 ,  G10L21/00

CPC分类号： H03M7/30

摘要： An audio decoder 100 for operating on a received compressed audio data stream compressed using an algorithm employing transform encoding and a bit allocation routine. A first processor 200 performs a first set of operations on the received compressed audio data stream including parsing the compressed audio data stream, recovering data fields within the compressed audio data stream, calculating a bit allocation, and passing frequency domain coefficients to shared memory. A second digital signal processor 100b performs a second set of operations on data passed from the first digital signal processor to shared memory including performing inverse transform operations on the data passed from the first digital signal processor.

摘要翻译： 一种音频解码器100，用于对使用采用变换编码的算法和位分配程序压缩的接收的压缩音频数据流进行操作。 第一处理器200对所接收的压缩音频数据流执行第一组操作，包括解析压缩音频数据流，恢复压缩音频数据流内的数据字段，计算比特分配，以及将频域系数传递给共享存储器。 第二数字信号处理器100b对从第一数字信号处理器传送到共享存储器的数据执行第二组操作，包括对从第一数字信号处理器传送的数据执行逆变换操作。

公开(公告)号：US5907263A

公开(公告)日：1999-05-25

申请号：US970841

申请日：1997-11-14

申请人： James Divine ,  Jeffrey Niehaus ,  John Pacourek ,  Baker Scott, III

发明人： James Divine ,  Jeffrey Niehaus ,  John Pacourek ,  Baker Scott, III

IPC分类号： H03L7/099

CPC分类号： H03L7/099

摘要： A voltage controlled oscillator with bias current calibration includes a voltage controlled oscillator 1504. A tuning current source 1510 is coupled to oscillator 1504 in parallel with bias current source 1512 for providing a tuning current to oscillator 1504. A selected control voltage is provided by oscillator 1504 for setting an oscillator output frequency. Control circuitry 1513, 1514 allows adjusting of the tuning current source to optimize bias current.

摘要翻译： 具有偏置电流校准的压控振荡器包括压控振荡器1504.调谐电流源1510与偏置电流源1512并联耦合到振荡器1504，用于向振荡器1504提供调谐电流。所选择的控制电压由振荡器1504 用于设置振荡器输出频率。 控制电路1513,1514允许调整调谐电流源以优化偏置电流。