公开(公告)号：US5907263A

公开(公告)日：1999-05-25

申请号：US970841

申请日：1997-11-14

申请人： James Divine ,  Jeffrey Niehaus ,  John Pacourek ,  Baker Scott, III

发明人： James Divine ,  Jeffrey Niehaus ,  John Pacourek ,  Baker Scott, III

IPC分类号： H03L7/099

CPC分类号： H03L7/099

摘要： A voltage controlled oscillator with bias current calibration includes a voltage controlled oscillator 1504. A tuning current source 1510 is coupled to oscillator 1504 in parallel with bias current source 1512 for providing a tuning current to oscillator 1504. A selected control voltage is provided by oscillator 1504 for setting an oscillator output frequency. Control circuitry 1513, 1514 allows adjusting of the tuning current source to optimize bias current.

摘要翻译： 具有偏置电流校准的压控振荡器包括压控振荡器1504.调谐电流源1510与偏置电流源1512并联耦合到振荡器1504，用于向振荡器1504提供调谐电流。所选择的控制电压由振荡器1504 用于设置振荡器输出频率。 控制电路1513,1514允许调整调谐电流源以优化偏置电流。

公开(公告)号：US6081783A

公开(公告)日：2000-06-27

申请号：US970979

申请日：1997-11-14

申请人： James Divine ,  Jeffrey Niehaus ,  Miroslav Dokic ,  Raghunath Rao ,  Terry Ritchie ,  Baker Scott, III ,  John Pacourek ,  Zheng Luo

发明人： James Divine ,  Jeffrey Niehaus ,  Miroslav Dokic ,  Raghunath Rao ,  Terry Ritchie ,  Baker Scott, III ,  John Pacourek ,  Zheng Luo

IPC分类号： H03M7/30 ,  G10L21/00

CPC分类号： H03M7/30

摘要： An audio decoder 100 for operating on a received compressed audio data stream compressed using an algorithm employing transform encoding and a bit allocation routine. A first processor 200 performs a first set of operations on the received compressed audio data stream including parsing the compressed audio data stream, recovering data fields within the compressed audio data stream, calculating a bit allocation, and passing frequency domain coefficients to shared memory. A second digital signal processor 100b performs a second set of operations on data passed from the first digital signal processor to shared memory including performing inverse transform operations on the data passed from the first digital signal processor.

摘要翻译： 一种音频解码器100，用于对使用采用变换编码的算法和位分配程序压缩的接收的压缩音频数据流进行操作。 第一处理器200对所接收的压缩音频数据流执行第一组操作，包括解析压缩音频数据流，恢复压缩音频数据流内的数据字段，计算比特分配，以及将频域系数传递给共享存储器。 第二数字信号处理器100b对从第一数字信号处理器传送到共享存储器的数据执行第二组操作，包括对从第一数字信号处理器传送的数据执行逆变换操作。

公开(公告)号：US06262616B1

公开(公告)日：2001-07-17

申请号：US09415136

申请日：1999-10-08

申请人： Vishnu S. Srinivasan ,  John Pacourek ,  John James Paulos

发明人： Vishnu S. Srinivasan ,  John Pacourek ,  John James Paulos

IPC分类号： G11C514

CPC分类号： H03F1/301 ,  H03F2200/331 ,  H03K5/133 ,  H03K2005/0013 ,  H03K2005/00202 ,  H03M3/458 ,  H03M3/50

摘要： A technique for compensating for supply voltage variations in a delay circuit by utilizing a bias circuit to maintain the delay substantially constant with respect to the supply voltage. The bias circuit generates a bias current having a fixed component and a variable component, in which the variable component varies proportionately to variations in the supply voltage to maintain the delay substantially constant.

摘要翻译： 一种用于通过利用偏置电路来补偿延迟电路中的电源电压变化以维持相对于电源电压基本恒定的延迟的技术。 偏置电路产生具有固定分量和可变分量的偏置电流，其中可变分量与电源电压的变化成比例地变化，以保持延迟基本恒定。

公开(公告)号：US07630464B1

公开(公告)日：2009-12-08

申请号：US11109301

申请日：2005-04-19

申请人： Frederic Deboes ,  John Pacourek ,  Tom Cook

发明人： Frederic Deboes ,  John Pacourek ,  Tom Cook

IPC分类号： H03D1/04 ,  H03M1/06 ,  H03M1/12

CPC分类号： H03M1/0607 ,  H03M1/36

摘要： Systems and methods are disclosed herein to provide analog-to-digital interface techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes an offset cancellation circuit provides offset cancellation for input signal paths under control of at least a first clock signal. A comparator, coupled to the offset cancellation circuit, provides an output signal based on a comparison of input signals provided on the input signal paths. A register receives the output signal and provides the output signal to a digital circuit under control of a first control signal, wherein the at least first clock signal is synchronized to a clock signal of the digital circuit.

摘要翻译： 本文公开了提供模拟到数字接口技术的系统和方法。 例如，根据本发明的实施例，集成电路包括偏移消除电路，用于在至少第一时钟信号的控制下为输入信号路径提供偏移消除。 耦合到偏移消除电路的比较器基于输入信号路径上提供的输入信号的比较来提供输出信号。 寄存器接收输出信号，并在第一控制信号的控制下向数字电路提供输出信号，其中至少第一时钟信号与数字电路的时钟信号同步。