公开(公告)号：US09639488B2

公开(公告)日：2017-05-02

申请号：US14310215

申请日：2014-06-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Gregory Sadowski ,  Sudha Thiruvengadam ,  Arun Iyer

IPC: G06F1/04 ,  G06F13/38 ,  G06F1/00 ,  H04L7/00

CPC classification number: G06F13/38 ,  G06F1/00 ,  G06F1/04 ,  G06F1/10 ,  H04L7/0008

Abstract: Embodiments are described for a method of reducing power consumption in source synchronous bus systems by reducing signal transitions in the system. Instead of sending clock and data valid signals, only the start and end of valid data packets are marked by clock signal transitions, or only a number of clock pulses that corresponds to number of data words is sent, or only a number transitions on clock signals are sent. The clock signal transitions may comprise either clock pulses or exclusively rising edge or falling edge transitions of the clock signal.

公开(公告)号：US20150372802A1

公开(公告)日：2015-12-24

申请号：US14310215

申请日：2014-06-20

Applicant: Advanced Micro Devices, Inc

Inventor： Gregory Sadowski ,  Sudha Thiruvengadam ,  Arun Iyer

IPC: H04L7/00 ,  H04L12/40

CPC classification number: G06F13/38 ,  G06F1/00 ,  G06F1/04 ,  G06F1/10 ,  H04L7/0008

Abstract: Embodiments are described for a method of reducing power consumption in source synchronous bus systems by reducing signal transitions in the system. Instead of sending clock and data valid signals, only the start and end of valid data packets are marked by clock signal transitions, or only a number of clock pulses that corresponds to number of data words is sent, or only a number transitions on clock signals are sent. The clock signal transitions may comprise either clock pulses or exclusively rising edge or falling edge transitions of the clock signal.

Abstract translation: 描述了通过减少系统中的信号转换来降低源同步总线系统中的功耗的方法的实施例。 而不是发送时钟和数据有效的信号，只有有效的数据包的开始和结束被标记为时钟信号转换，或者仅发送对应于数据字的数量的多个时钟脉冲，或者只有时钟信号上的数字转换 被发送。 时钟信号转换可以包括时钟脉冲或专用时钟信号的上升沿或下降沿转换。