公开(公告)号：US11789075B1

公开(公告)日：2023-10-17

申请号：US17853409

申请日：2022-06-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Nur Mohammad Baksh ,  Michael Q. Co ,  Vibhor Mittal ,  Kedar Karthykeyan

IPC: G01R31/3177 ,  G01R31/3185 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31727 ,  G01R31/318541 ,  G01R31/318552

Abstract: A method includes generating a functional clock signal, a scan clock signal, and a delayed clock signal based on a control clock signal and a scan enable signal. The method includes precharging or predischarging a differential pair of nodes in a first latch using the delayed clock signal and a voltage on a first power supply node and controlling a second latch using the delayed clock signal. The method includes latching data input by the first latch using the functional clock signal in a functional mode of operation and latching scan data by the first latch using the scan clock signal in a scan mode of operation.