公开(公告)号：US11095274B1

公开(公告)日：2021-08-17

申请号：US17032530

申请日：2020-09-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Nur Mohammad Baksh ,  Michael Q. Co

IPC: H03K3/0233 ,  H03K3/037 ,  H03K3/3562

Abstract: A pre-discharged edge-triggered flip-flop, in which internal nodes determinative of an output signal are discharged to VSS prior to an evaluation phase of a clock signal, is provided to enable improved clock-to-output response times when provided with a rising edge of a clock pulse. In operation, during a pre-discharge phase of the clock signal, multiple internal nodes of a differential master latch circuit of the flip-flop are discharged to VSS. In response to a rising edge of the clock signal signaling the beginning of an evaluation phase, one of the internal nodes (selected depending on the logical value of an input signal to the flip-flop) is charged to VDD while other of the internal nodes remain at VSS. A single clock signal inverter is disposed between the input clock signal and a multiplexer providing the output data signal.

公开(公告)号：US11789075B1

公开(公告)日：2023-10-17

申请号：US17853409

申请日：2022-06-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Nur Mohammad Baksh ,  Michael Q. Co ,  Vibhor Mittal ,  Kedar Karthykeyan

IPC: G01R31/3177 ,  G01R31/3185 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31727 ,  G01R31/318541 ,  G01R31/318552

Abstract: A method includes generating a functional clock signal, a scan clock signal, and a delayed clock signal based on a control clock signal and a scan enable signal. The method includes precharging or predischarging a differential pair of nodes in a first latch using the delayed clock signal and a voltage on a first power supply node and controlling a second latch using the delayed clock signal. The method includes latching data input by the first latch using the functional clock signal in a functional mode of operation and latching scan data by the first latch using the scan clock signal in a scan mode of operation.

公开(公告)号：US09606177B2

公开(公告)日：2017-03-28

申请号：US14716215

申请日：2015-05-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Daniel W. Bailey ,  Abhishek Sharma ,  Michael Q. Co

IPC: H03K3/00 ,  G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31727 ,  G01R31/318525 ,  G01R31/318552

Abstract: In one form, a scan flip-flop includes a clock gating cell and a dedicated clock flip-flop. The clock gating cell provides an input clock input signal as a scan clock signal when a scan shift enable signal is active, and provides the input clock signal as a data clock signal when the scan shift enable signal is inactive. The dedicated clock flip-flop stores a data input signal and provides the data input signal, so stored, as a data output signal in response to transitions of the data clock signal, and stores a scan data input signal and provides the scan data input signal, so stored, as the data output signal in response to transitions of the scan clock signal. The clock gating cell may further provide the input clock signal as the data clock signal when both a scan shift enable signal is inactive and a data enable signal is active.

公开(公告)号：US20160341793A1

公开(公告)日：2016-11-24

申请号：US14716215

申请日：2015-05-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Daniel W. Bailey ,  Abhishek Sharma ,  Michael Q. Co

IPC: G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31727 ,  G01R31/318525 ,  G01R31/318552

Abstract: In one form, a scan flip-flop includes a clock gating cell and a dedicated clock flip-flop. The clock gating cell provides an input clock input signal as a scan clock signal when a scan shift enable signal is active, and provides the input clock signal as a data clock signal when the scan shift enable signal is inactive. The dedicated clock flip-flop stores a data input signal and provides the data input signal, so stored, as a data output signal in response to transitions of the data clock signal, and stores a scan data input signal and provides the scan data input signal, so stored, as the data output signal in response to transitions of the scan clock signal. The clock gating cell may further provide the input clock signal as the data clock signal when both a scan shift enable signal is inactive and a data enable signal is active.

Abstract translation: 在一种形式中，扫描触发器包括时钟门控单元和专用时钟触发器。 当扫描移位使能信号有效时，时钟门控单元提供输入时钟输入信号作为扫描时钟信号，并且当扫描移位使能信号无效时，时钟门控单元提供输入时钟信号作为数据时钟信号。 专用时钟触发器存储数据输入信号，并且响应于数据时钟信号的转变而提供数据输入信号，从而存储数据输入信号作为数据输出信号，并存储扫描数据输入信号并提供扫描数据输入信号 ，因此存储，作为响应于扫描时钟信号的转变的数据输出信号。 当扫描移位使能信号无效且数据使能信号有效时，时钟门控单元还可以提供输入时钟信号作为数据时钟信号。